Register allocation methods having upward pass for determining and propagating variable usage information and downward pass for binding; both passes utilizing interference graphs via coloring

• US 5,530,866 A
• Filed: 10/13/1994
• Issued: 06/25/1996
• Est. Priority Date: 07/30/1991
• Status: Expired due to Term

• Current Assignee: Tera Computer Company (Hewlett-Packard Enterprise Company)
• Original Assignee: Tera Computer Company (Hewlett-Packard Enterprise Company)
• Inventors: Callahan, Charles D. II, Koblenz, Brian D.
• Primary Examiner(s): Oberley, Alvin E.
• Assistant Examiner(s): BACKENSTOSE, JONATHAN
• Application Number:
  US08/324,152
• Time in Patent Office: 621 Days
• Field of Search: 395/700, 395/375, 364/280, 364/280.4, 364/280.5, 364/281.6
• US Class Current: 717/144
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space

Abstract

The present invention provides methods for allocating physical registers within a compiler phase to achieve efficient operation of a target CPU. The methods of the present invention allocate variables between physical registers and memory to accommodate local as well as global code structure. Such methods facilitate the location of variables that are heavily accessed at a portion of the code in a physical register during the execution thereof.

Claims

1. A computer-implemented method for allocating variables among physical registers of a target computer during conversion of a higher level code portion to a form readable by the target computer, comprising the steps of:

generating a hierarchical tile tree corresponding to an underlying control structure of the code portion and including a root tile having a first code block with no predecessor and a second code block with no successor and a set of basic tiles corresponding to at least one of loop control structures and conditional control structures, the root tile being hierarchically superior to the basic tiles and at least a first one of the basic tiles being hierarchically superior to at least a second one of the basic tiles;

determining variable usage within the tiles beginning with hierarchically inferior tiles and proceeding to hierarchically superior tiles, the variable usage for hierarchically superior tiles including summary variable usage of hierarchically inferior tiles;

assigning variables to a number of pseudo registers based upon the variable usage within the tile for each tile, the number of pseudo registers being limited by the number of physical registers;

determining variable usage within the code section for each tile beginning with hierarchically superior tiles and proceeding to hierarchically inferior tiles, the variable usage for hierarchically inferior tiles including variable usage of hierarchically superior tiles; and

binding the pseudo registers to the physical registers such that conflicts between variables used within a tile and variables used in the code section outside of the tile are resolved to reduce variable usage costs within the entire code section.

2. A variable allocation method according to claim 1 further including the step of inserting spill code at a location in the code portion which minimizes spill code execution frequency.

3. A variable allocation method according to claim 1 wherein the assigning and binding steps are conducted in accordance with local weights based on estimates of the number of references to variables in the code portion.

4. A variable allocation method according to claim 1, where the assigning and binding steps are conducted using profiling information to achieve variable allocation enhancement.

5. A variable allocation method according to claim 1 wherein two code portions represented by separate tiles in the hierarchical tile tree may be processed simultaneously.

6. A variable allocation method according to claim 5 wherein the separate tiles representing the two code portions are at the same level in the hierarchical tile tree.

7. A variable allocation method according to claim 1 wherein the assigning step comprises generating a plurality of local interference graphs, each graph corresponding to a tile in the hierarchical tile tree, thereby decreasing resource requirements for implementation of the method.

8. A variable allocation method according to claim 7, wherein the interference graph for each tile comprises variables local to the tile, global variables accessed within the tile and a set of tile summary variables for each child tile of the tile.

9. A variable allocation method according to claim 1 further comprising the step of using one or more temporary registers to deliver one or more operands of target computer instructions to achieve variable allocation without iteration of the allocation method.

10. A variable allocation method according to claim 1, which further comprises the step of preferencing two or more variables to the same register without permanently binding the variables together so that the variables cannot undergo further processing separately.

11. A variable allocation method according to claim 10 wherein preferencing information is propagated up the hierarchical tile tree during the assignment step.

12. A variable allocation method according to claim 10 wherein the code portion includes an assignment between the variables to be preferenced.

13. A variable allocation method according to claim 1 further comprising the step of preferencing a variable to a physical register in which the variable is required to be resident.

14. A variable allocation method according to claim 13 wherein the variable is allocated to the required physical register during the assignment step.

15. A variable allocation method according to claim 1 in which tiles in the hierarchical tile tree are in levels that have a parent and child relationship wherein a register to memory transfer of a variable between a parent tile and a child tile is conducted only if it results in fewer total register to memory variable transfers when the code portion is compiled.

16. A variable allocation method according to claim 1 in which tiles in the hierarchical tile tree are in levels that have a parent and child relationship wherein a register to memory transfer of a variable between a parent tile and a child tile is not conducted at an exit edge of the child tile if the variable is used but not modified in the child tile.

17. A variable allocation method according to claim 1 further including the step of inserting spill code at a location other than at an entry or exit edge of the tile for which a decision to spill a variable has been made.

18. A variable allocation method according to claim 17 wherein spill code to achieve a memory to register transfer of a variable is inserted at a lower level in the hierarchical tile tree than dictated by register pressure to minimize an execution frequency of the spill code.

19. A variable allocation method according to claim 17 wherein spill code to achieve a register to memory transfer of a variable is inserted at a higher level in the hierarchical tile tree than dictated by register pressure, because the variable is not allocable to a register lower in the hierarchical tile tree and benefit garnered by having the variable in a register higher in the tile tree is not great.

20. The method of claim 1 in which the local variable usage is determined by scanning the hierarchical tile tree in a bottom-up direction starting with a leaf tile which is hierarchically superior to no other tile, and the global variable usage is determined by scanning the hierarchical tile tree in a top-down direction starting with the root tile.

21. The method of claim 1 in which determining variable usage within the tiles includes determining a first interference graph for variables within each tile and in which determining variable usage within the code section includes determining a second interference graph for variables in each tile.

22. The method of claim 1 in which the program code can be represented by a control flow graph, G=(B,E), where B represents a set of basic code blocks, E represents a set of control flow edges between elements of B, and in which generating a tile tree includes generating a tile tree, T, defined as a collection of sets of basic blocks encompassing the entire set B in which each element of T, t, defined as a tile, meets the following requirements:

(1) each pair of sets t in T are either disjoint or one is a proper subset of the other and if t₂ ε

t₁ and there is no tε

T such that t₂ ε

tε

t₁, then t₂ is a child tile or subtile of t₁ and t₁ is the parent tile of t₂, denoted t₁ =parent(t₂), the set blocks(t) being defined to be the set of basic blocks that are members of t but are not members of any child of t;

(2) for each edge e=(n,m)ε

E and tile t such that mε

t, either nε

t or nε

blocks(parent(t)); and

(3) For each edge e=(m,n)ε

E and tile t such that mε

t, either nε

t or nε

blocks(parent(t)).

23. The method of claim 1 in which determining variable usage within the code section includes creating an interference graph that includes global variables that are live, but not used, within the tile.

24. A computer-implemented method for allocating variables among physical registers and a separate memory of a target computer during conversion of a higher level code portion to a form readable by the target computer, comprising the steps of:

generating a hierarchical tile tree that corresponds to an underlying control structure of the code portion and including a root the having a first code block with no predecessor and a second code block with no successor and a set of basic tiles corresponding to at least one of loop control structures and conditional control structures, the root tile being hierarchically superior to the basic tiles and at least a first one of the basic tiles being hierarchically superior to at least a second one of the basic tiles;

determining variable usage within tiles for the tiles beginning with hierarchically inferior tiles and proceeding to hierarchically superior tiles, the variable usage within tiles for hierarchically superior tiles including summary variable usage of hierarchically inferior tiles;

determining variable usage globally within the code portion for the tiles beginning with hierarchically superior tiles and proceeding to hierarchically inferior tiles, the variable usage for hierarchically inferior tiles including variable usage of hierarchically superior tiles;

allocating variables to physical registers response to the vocal variable usage and the global variable such that conflicts among variables within individual tiles and variables used in the code portion outside the tile are resolved to reduce variable usage costs; and

inserting code to spill to the memory variables not allocated to physical registers.

25. The method of claim 24 in which the underlying control structure of the code portion includes a conditional structure, and the method further comprises the step of inserting spill code inside the conditional structure.

26. The method of claim 24 in which spill code is inserted after determining variable usage globally within the code portion and allocating variables to physical registers.

27. A computer-implemented method for allocating variables among physical registers of a target computer during conversion of a higher level code portion to a form readable by the target computer, comprising the steps of:

generating a hierarchical tile tree corresponding to an underlying control structure of the code portion, the hierarchical tile tree defining parent-child relationships among the tiles;

determining during a first phase variable usage within the tiles beginning with hierarchically inferior tiles and proceeding to hierarchically superior tiles, the variable usage within the tiles being determined by;

constructing and coloring a tile interference graph to identify conflicts within each leaf tile, the interference graphs incorporating preference information;

assigning in accordance with the interference graph coloring variables to pseudo registers and tentatively designating variables that cannot be assigned to pseudo registers to spill, the number of pseudo registers being limited by the number of physical registers;

constructing and coloring tile interference graphs to identify conflicts within hierarchically superior tiles and, for each hierarchically superior tile, designating variables to be assigned to pseudo registers or to be spilled, the designation determined by the variable usage within each hierarchically superior tile and within its child tiles, the interference graph for each hierarchically superior tile incorporating preference information and tile summary variables from its child tiles, the number of summary variables being limited by the number of pseudo registers;

determining in a second phase variable usage within the code section beginning with hierarchically superior tiles and proceeding to hierarchically inferior tiles, the variable usage within the tiles of the code section being determined by;

constructing and coloring tile interference graphs to identify conflicts within each hierarchically inferior tile and, for each hierarchically inferior tile, designating variables used within the tile or that are live across the tile to be assigned to physical registers or to be spilled, the designation determined by the variable usage within the tile and by the register allocation in the corresponding parent tile and the interference graph for each hierarchically inferior tile incorporating preference information from itself and its parent tiles;

inserting spill code at tile entry or exit edges if all variables cannot be assigned to physical registers, the assignment of variables to physical registers reducing variable usage costs within the entire code section.

28. The method of claim 27 in which each tile summary variable corresponds to a set of variables that are used within a child tile and that are assigned to the same pseudo register.

29. The method of claim 27 in which the interference graphs constructed in the first phase include variables referenced in the tile and in which the interference graphs constructed in the second phase include variables referenced in the tile and global variables that are live across the tile.

30. The method of claim 27 in which a linkage convention requires a procedure call or result to be stored in a specific register and in which a variable corresponding to the procedure call or result is preferenced to the specific physical register by assigning the variable to the register within the corresponding tile if the physical register is available.

31. The method of claim 27 in which variables that are related by a simple assignment statement are preferenced to each other by assigning to the variables the same color as their preference within the tile containing the assignment statement, thereby reducing variable moves between registers.

32. The method of claim 27 further comprising maintaining a summary of variable conflicts between tiles.

33. The method of claim 27 in which the spill code includes instructions to spill variables to memory, instructions to transfer variables between registers, or instructions to reload code from memory.

34. The method of claim 27 in which the spill code is inserted at an edge of a tile other than the tile at which the determination to spill the variable is made.