Method of making subsurface electronic circuits

• US 5,531,020 A
• Filed: 08/27/1993
• Issued: 07/02/1996
• Est. Priority Date: 11/14/1989
• Status: Expired due to Term

• Current Assignee: Parlex USA, Inc.
• Original Assignee: Poly-Flex Circuits Incorporated
• Inventors: Durand, David, Iannetta, Roger A. Jr.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/112,225
• Time in Patent Office: 1,040 Days
• Field of Search: 29/840, 29/846, 29/848, 427/96, 174/260, 264/61
• US Class Current: 29/840
• CPC Class Codes: C08L 2666/54 Inorganic substances
• CPC Class Codes: C09J 163/00 Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
• CPC Class Codes: H01B 1/22 the conductive material comprising metals or alloys
• CPC Class Codes: H01L 21/4867 Applying pastes or inks, e.g. screen printing H01L21/486 takes precedence
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29399 Coating material
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01R 4/04 : using electrically conductive adhesives
• CPC Class Codes: H05K 1/095 : for polymer thick films, i.e. having a permanent organic polymeric binder
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/0125 : Shrinkable, e.g. heat-shrinkable polymer
• CPC Class Codes: H05K 2201/0218 : Composite particles, i.e. first metal coated with second metal
• CPC Class Codes: H05K 2201/023 : Hard particles, i.e. particles in conductive adhesive at least partly penetrating an electrode
• CPC Class Codes: H05K 2201/0245 : Flakes, flat particles or lamellar particles
• CPC Class Codes: H05K 2201/0272 : Mixed conductive particles, i.e. using different conductive particles, e.g. differing in shape
• CPC Class Codes: H05K 2201/09036 : Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2203/0307 : Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
• CPC Class Codes: H05K 2203/0568 : Resist used for applying paste, ink or powder
• CPC Class Codes: H05K 2203/1105 : Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
• CPC Class Codes: H05K 2203/1453 : Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors
• CPC Class Codes: H05K 3/0023 : by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/107 : by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/1258 : by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
• CPC Class Codes: H05K 3/28 : Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673
• CPC Class Codes: H05K 3/321 : by conductive adhesives
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A method of making a planar, subsurface electronic circuit having at least one electronic circuit component assembled therewith is disclosed. First, three dimensional, essentially square channels interspersed with lands are formed within a dielectric material on a substrate. The channels are then filled in one pass with a curable polymeric material containing a conductive metal filler so that the upper surfaces of the circuit trace formed by this conductive material are at essentially the same level as the upper surface of the lands. Circuit components are place to engage the conductive material. The curable material is then cured after placing the electronic component(s).

Claims

1. A method of making electronic circuits in a rigid dielectric substrate comprising steps of:

(a) forming a channel within a dielectric substrate;

(b) screening a curable conductive material into the channel to form an uncured circuit trace;

(c) placing circuit components in engagement with the uncured circuit trace; and

(d) curing the curable conductive material after placing the circuit components, thereby creating a circuit trace which electrically connects the circuit components;

wherein the channel forming step includes steps of;

i) applying a layer of photoimagable material on to the substrate,

ii) exposing the photoimagable material with an image corresponding to the circuit trace, and

iii) developing the photoimagable material, thereby leaving a channel in the layer of photoimagable material.

2. A method of making electronic circuits in a rigid dielectric substrate comprising steps of:

(a) forming a channel within a dielectric substrate;

(b) screening a curable conductive material into the channel to form an uncured circuit trace;

(c) placing circuit components in engagement with the uncured circuit trace; and

(d) curing the curable conductive material after placing the circuit components, thereby creating a circuit trace which electrically connects the circuit components;

wherein the channel forming step includes steps of;

i) forming a first portion of the circuit trace in a first layer of the substrate;

ii) forming a channel in a second layer of the substrate, the channel overlapping a region of the first portion of the circuit trace.

3. A method of making electronic circuits in a rigid dielectric substrate comprising steps of:

(a) forming a channel within a dielectric substrate;

(b) filling the channel with a curable conductive material to form an uncured circuit trace;

(c) placing circuit components in engagement with the uncured circuit trace; and

(d) curing the curable conductive material after placing the circuit components, thereby creating a circuit trace which electrically connects the circuit components;

wherein the channel forming step includes a step of forming a removable layer on the substrate around the periphery of the channel, and the channel filling step comprises steps of;

i) spreading the curable conductive material across the removable layer and into the channel, and

ii) removing the removable layer while leaving curable conductive material in the channel.

4. A method of making electronic circuits in a rigid dielectric substrate comprising steps of:

(a) forming a channel within a dielectric substrate;

(b) screening a curable conductive material into the channel to form an uncured circuit trace;

(c) placing circuit components in engagement with the uncured circuit trace; and

(d) curing the curable conductive material after placing the circuit components, thereby creating a circuit trace which electrically connects the circuit components;

wherein the channel forming step includes a step of forming a removable layer on the substrate around the periphery of the channel, and the channel filling step comprises steps of;

i) spreading the curable conductive material across the removable layer and into the channel, and

ii) washing away the removable layer with a solvent while leaving curable conductive material in the channel.

5. The method of claim 4 wherein the washing step includes a step of spraying solvent onto the substrate with a nozzle.

7. The method of claim 4, wherein steps (a) to (f) are performed after first forming a first conductive trace in the substrate, and steps (a) to (f) form a second conductive trace above and in electrical contact with the first conductive trace, thereby forming a multi-layer circuit.

6. A method of making electronic circuits in rigid dielectric substrates comprising steps of:

(a) applying a layer of photoimagable material on to a substrate,

(b) exposing the photoimagable material with an image corresponding to a circuit trace,

(c) developing the photoimagable material, thereby leaving a channel in the layer of photoimagable material;

(d) screening curable conductive material into the channel through a screen having a pattern matching the channel to form an uncured circuit trace;

(e) placing circuit components in engagement with the uncured circuit trace; and

(f) curing the curable conductive material after placing the circuit components, thereby creating a cured circuit trace which electrically connects the circuit components.

8. The method of claim 6 wherein the curing step includes a step of curing at a temperature below about 180 degrees C.

9. The method of claim 6 wherein the curing step includes a step of curing at a temperature between about 130 degrees C. and about 180 degrees C.

10. The method of claim 6 wherein the component placement step includes a step of placing a surface mount device.

11. The method of claim 6 wherein the component placement step includes a step of placing a flip chip.