Cube wireability enhancement with chip-to-chip alignment and thickness control

• US 5,532,519 A
• Filed: 01/20/1995
• Issued: 07/02/1996
• Est. Priority Date: 09/14/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Cronin, John E., Perlman, David J.
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/375,770
• Time in Patent Office: 529 Days
• Field of Search: 257/777, 257/486, 257/685, 257/684, 257/623, 257/775, 257/797, 257/700, 257/723, 257/730
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Claims

1. An electronic module comprising:

two integrated circuit chips, said two integrated circuit chips being stacked in said electronic module;

a first of the two integrated circuit chips having a first thickness control layer formed integrally therein, a thickness of said first thickness control layer determined as a function of the thickness of at least a portion of the first integrated circuit chip.

2. The electronic module of claim 1, further comprising:

a third integrated circuit chip such that three integrated circuit chips are stacked in said electronic module;

the third integrated circuit chip having a second thickness control layer formed integrally therein, a thickness of said second thickness control layer determined as a function of the thickness of at least a portion of the third integrated circuit chip such that a distance measured between any two of the three integrated circuit chips is substantially a multiple of a distance measured between two adjacent integrated circuit chips in said electronic module.

3. The electronic module of claim 2, further comprising:

electrically conducting pads disposed on exposed edge faces of two of said three integrated circuit chips; and

an electrical wiring network connected to selected ones of said pads for delivering electrical signals between said two integrated circuit chips or between said electronic module and at least one external device.

4. The electronic module of claim 1, wherein:

said first thickness control layer has a pattern etched thereon, said pattern including a projection; and

said second one of said two integrated circuit chips has a complementary pattern etched thereon, said complementary pattern including a recess formed at a position corresponding to said projection, said recess interlocking with said projection, said first and second ones of said two integrated circuit chips being thereby controllably positioned in said electronic module.

5. The electronic module of claim 4, further comprising:

a third layer disposed between said first one and said second one of said two integrated circuit chips, and wherein said complementary pattern is etched into said third layer.

6. An electronic module comprising:

a plurality of stacked integrated circuit chips, at least one of said plurality of stacked integrated circuit chips having integrally formed therein means for controlling a distance between a portion of the at least one stacked integrated circuit chip and a respective portion of another of said plurality of stacked integrated circuit chips; and

means for laterally aligning at least two adjacent ones of said plurality of stacked integrated circuit chips.

7. The electronic module of claim 6, wherein said distance controlling means comprises a layer formed integrally within the at least one of said plurality of stacked integrated circuit chips, said layer having a thickness determined from a measured thickness of at least a portion of said at least one of said plurality of stacked integrated circuit chips.

8. The electronic module of claim 6, wherein said laterally aligning means comprises complementary interlocking patterns disposed between the at least two adjacent ones of said plurality of stacked integrated circuit chips.

9. The electronic module of claim 6, further comprising:

a plurality of electrically conductive pads disposed on exposed edge faces of selected ones of said plurality of stacked integrated circuit chips; and

an electrical wiring network contacting selected ones of said plurality of electrically conductive pads.

10. The electronic module of claim 7, wherein said laterally aligning means comprises complementary interlocking patterns disposed between the at least two adjacent ones of said plurality of stacked integrated circuit chips.

11. The electronic module of claim 10, wherein the at least two adjacent ones of said plurality of stacked integrated circuit chips comprises the at least one of said plurality of stacked integrated circuit chips and wherein at least one of said complementary interlocking patterns is provided in said layer.

12. An integrated circuit chip to be stacked in a three dimensional electronic module, said integrated circuit chip comprising:

a thickness control layer formed integrally therein, the thickness of the thickness control layer being determined during the fabrication of the integrated circuit chip as a function of the thickness of at least a portion of the integrated circuit chip.

13. An electronic module comprising a plurality of integrated circuit chips stacked therein, each of at least a portion of the plurality of integrated circuit chips stacked therein being formed according to claim 12.

17. The electronic module of claim 13, wherein at least some of the plurality of integrated circuit chips have conductive pads disposed on exposed edge faces thereof, and wherein the electronic module further comprises:

an electrical wiring network disposed along said exposed edge faces

and contacting at least some of said conductive pads.

14. A three dimensional electronic module having a plurality of stacked integrated circuit chips therein, wherein:

a first integrated circuit chip of the plurality of stacked integrated circuit chips has a main surface with at least one recess therein; and

a second integrated circuit chip of the plurality of stacked integrated circuit chips has a main surface adjacent the main surface of the first integrated circuit chip, a portion of the main surface of the second integrated circuit chip being disposed over the recess;

the three dimensional electronic module further comprising an adhesive disposed in said recess for fastening said first integrated circuit chip to the portion of the main surface of the second stacked integrated circuit chip, the adhesive thereby not increasing the distance between the first and second integrated circuit chips in the module.

15. The three dimensional electronic module of claim 14, wherein the second integrated circuit chip has a thickness control layer integrally formed therein, the thickness of the thickness control layer being determined as a function of at least a portion of the second integrated circuit chip.

16. The three dimensional electronic module of claim 14, wherein the portion of the main surface of the second stacked integrated circuit chip disposed over said recess includes a projection disposed at least partially within said recess.