Multilevel converter with capacitor voltage balancing

• US 5,532,575 A
• Filed: 01/06/1995
• Issued: 07/02/1996
• Est. Priority Date: 01/08/1994
• Status: Expired due to Fees

• Current Assignee: Alstom Uk
• Original Assignee: GEC Alsthom Limited (GE Vernova, Inc.)
• Inventors: Ainsworth, John D., Trainer, David R.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Krishnan, Aditya
• Application Number:
  US08/369,474
• Time in Patent Office: 543 Days
• Field of Search: 363/39, 363/40, 363/44, 363/79-82, 323/209-211
• US Class Current: 323/211
• CPC Class Codes: H02J 3/1857 wherein such bridge converter is a multilevel converter
• CPC Class Codes: H02M 7/162 in a bridge configuration
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: Y02E 40/10 Flexible AC transmission systems [FACTS]
• CPC Class Codes: Y02E 40/20 Active power filtering [APF]
• CPC Class Codes: Y02E 40/30 Reactive power compensation

Abstract

A multilevel convertor having a set of series-connected capacitors and a set of associated series-connected switching elements employs a main control loop which controls some aspect of an AC system, e.g. busbar voltage, by controlling the switching times of the switching elements. The convertor also comprises one or more subsidiary control loops for establishing a desired relationship between mean DC voltage levels on the capacitors. The subsidiary control loops combine first signals proportional to DC voltage levels on the capacitors and second signals proportional to tap currents associated with the capacitor nodes to provide signals which modulate the timing of the switching of switching elements connected to those capacitors which are out of balance, while leaving alone the timing of the switching of switching elements associated with those capacitors which have the required voltage across them. The advantage of the invention is that it prevents the "run-away" of individual capacitor voltages to values grossly in error, the run-away being due either to spontaneous instability or to temporary disturbances.

Claims

1. A multilevel convertor for connection to a single-phase or multiphase AC system, the convertor comprising:

a plurality of series-connected capacitors, the capacitors being arranged, when the convertor is switched on, to be charged to an initial DC voltage,

a plurality of switch means for each phase for connecting each node of the plurality of capacitors in turn onto the AC system, said switch means having respective control inputs,

a main control loop arrangement for controlling the timing of the coupling of each node of the plurality of capacitors in turn onto the AC system, the main control loop arrangement including, for each phase;

a switching control means for performing switching operations on said switch means, said switching control means having a control input and a plurality of outputs connected to respective control inputs of said switch means,

an error signal producing means for producing an error signal representative of a difference between an actual value of an electrical quantity to be controlled and a reference value of said quantity, an output of said error signal producing means being connected to said control input of said switching control means,

a plurality of subsidiary control loops for each phase, said plurality of subsidiary control loops being one fewer in number than said plurality of capacitors and being associated with respective pairs of said capacitors, each subsidiary control loop including a first combining means having a first input for receiving a first signal proportional to a difference between mean DC voltage levels on a pair of capacitors associated with that subsidiary control loop, and a second input for receiving a second signal proportional to tap currents entering a pair of nodes associated with said pair of capacitors, the first combining means having an output which is taken to an input of said error signal producing means such that said output signal of said first combining means is additively combined with said error signal, said subsidiary control loops serving to maintain a predetermined relationship between the mean DC voltage levels on said plurality of capacitors.

4. The multilevel convertor as claimed in claim 1 or claim 2, in which the switching control means includes a voltage-controlled oscillator having a control input for receiving said error signal, and a sequencing means fed from an output of the voltage-controlled inputs of said switch means.

5. The multilevel convertor as claimed in claim 1 or claim 2, in which the first combining means is a multiplier.

6. The multilevel convertor as claimed in claim 1, in which each subsidiary control loop includes a second combining means having an output connected to the second input of the first combining means and first and second inputs for receiving first and second signals proportional to respective said tap currents.

7. The multilevel convertor as claimed in claim 6, in which each subsidiary control loop includes a weighting means in one or both of the first and second inputs of the second combining means.

8. The multilevel convertor as claimed in claim 7, in which the second combining means and the weighting means are configured such that, when the convertor is in operation, a signal at the output of the second combining means consists of the difference between one of the first and second signals proportional to tap currents and substantially twice the other of the first and second signals proportional to tap currents.

9. The multilevel convertor as claimed in claim 1, in which said second signal proportional to tap currents is derived by way of sensing means for sensing current flowing in the inductance means, the subsidiary control loops including respective strobing means for enabling the current sensed in the sensing means to be passed on to subsequent circuitry as the second signal proportional to tap currents at those times when the current flowing through the inductance means corresponds to the capacitor tap currents associated with the respective pair of capacitors.

11. The multilevel convertor as claimed in claim 4, in which the sequencing means includes a binary counter having a clocking input fed from the output of the voltage-controlled oscillator and a plurality of binary outputs, and a read-only memory having a plurality of address inputs fed from respective binary outputs of the counter, a plurality of storage locations and a plurality of data outputs which are arranged to switch the switching arrangement according to a pattern of data stored in the addressed storage locations.

12. The multilevel convertor as claimed in claim 1 or claim 2, in which the plurality of switch means includes a plurality of series-connected first switch means and a like plurality of series-connected second switch means, the plurality of first switch means being connected in series with the plurality of second switch means across the outermost nodes of the plurality of capacitors, and a plurality of first diodes and a like plurality of second diodes, the plurality of first switch means having tapping points which are connected by means of respective first diodes to respective tapping points of the plurality of capacitors and the plurality of second switch means having tapping points which are connected by means of respective second diodes to the same respective tapping points of the plurality of capacitors, the second diodes being configured in a reverse direction to the first diodes, and the inductance means being constituted by the leakage reactance of a voltage transformer arranged to link the convertor with the AC system.

13. The multilevel convertor as claimed in claim 12, in which the number of capacitors is n, the number of first and second switch means per phase is 2n, the number of first and second diodes per phase is n-1 and the number of voltage levels in the voltage presented to the AC system is n+1.

14. The multilevel convertor as claimed in claim 13, in which the transformer is a single-phase transformer, n is an even number, and a secondary winding of the transformer is connected at one end to the junction of the pluralities of first and second switch means and at the other end to the center tap of the plurality of capacitors.

15. The multilevel convertor as claimed in claim 13, in which the transformer is a single-phase transformer and in which is included a plurality of third switch means and a like plurality of fourth switch means, the third and fourth switch means being configured in the same way as the first and second switch means and being connected to the same respective capacitor tapping points by way of respective pluralities of third and fourth diodes, a secondary winding of the transformer being connected at one end to the junction of the pluralities of first and second switch means and at the other end to the junction of the pluralities of third and fourth switch means, the sequencing means being arranged to switch the third and fourth switch means in opposite phase with the first and second switch means.

16. The multilevel convertor as claimed in claim 13, in which the transformer is a three-phase transformer and in which is included a plurality of third switch means and like pluralities of fourth, fifth and sixth switch means, the third and fourth switch means and the fifth and sixth switch means being configured in the same way as the first and second switch means and being connected to the same respective capacitor tapping points by way of respective pluralities of third, fourth, fifth and sixth diodes, the transformer having first, second and third secondary phase windings which are connected to the junction of the pluralities of first and second switch means, the junction of the pluralities of third and fourth switch means and the junction of the pluralities of fifth and sixth switch means respectively, the switching control means being triplicated in order independently to control the switching of the first and second, the third and fourth, and the fifth and sixth switch means.

17. The multilevel convertor as claimed in claim 16, in which the first, second and third secondary phase windings are configured in star or in delta, the line voltage terminals of the star or delta configuration being connected to respective junctions of the pluralities of first and second switch means, the pluralities of third and fourth means and the pluralities of fifth and sixth switch means.

18. The multilevel convertor as claimed in claim 1 or claim 2, in which the switching means are any of:

gate-turn-off thyristors, bipolar transistors, field-effect transistors, MOS-controlled thyristors and insulated-gate bipolar transistors.

19. The multilevel convertor as claimed in claim 1 or claim 2, in which the main control loop arrangement is arranged to control any of:

the AC system voltage, the current passing through the inductance means and the admittance of the multilevel convertor as seen from the AC system.

20. A static Var compensator comprising the multilevel convertor according to claim 1 or claim 2, the convertor being arranged to draw adjustable leading or lagging reactive power from the AC system.

21. An AC-AC coupling arrangement comprising two multilevel convertors according to claim 1 or claim 2, the convertors being connected back-to-back so that they share a common set of capacitors.

22. A multilevel convertor arrangement comprising a plurality of multilevel convertors according to claim 1 or claim 2, in which the multilevel convertors are configured in parallel for connection to an AC system, the respective switching means of the convertors being arranged to be switched at different times so as to provide the equivalent of a single multilevel convertor having a number of levels approximately equal to the sum of the levels of each individual convertor.

2. A multilevel convertor for connection to a single-phase or multiphase AC system, the convertor comprising:

a plurality of series-connected capacitors, the capacitors being arranged, when the convertor is switched on, to be charged to an initial DC voltage,

a plurality of switch means for each phase for connecting each node of the plurality of capacitors in turn onto the AC system, said switch means having respective control inputs,

a main control loop arrangement for controlling the timing of the coupling of each node of the plurality of capacitors in turn onto the AC system, the main control loop arrangement including, for each phase;

a switching control means for performing switching operations on said switch means, said switching control means having a control input and a plurality of outputs connected to respective control inputs of said switch means,

an error signal producing means for producing an error signal representative of a difference between an actual value of an electrical quantity to be controlled and a reference value of said quantity, an output of said error signal producing means being connected to said control input of said switching control means,

a plurality of subsidiary control loops for each phase, said plurality of subsidiary control loops being the same in number as said plurality of capacitors and being associated with respective ones of said capacitors, each subsidiary control loop including a first combining means having a first input for receiving a first signal proportional to a difference between a mean DC voltage level on a capacitor associated with that subsidiary control loop and a reference voltage level, and a second input for receiving a second signal proportional to a tap current entering a node associated with said capacitor, the first combining means having an output which is taken to an input of said error signal producing means such that said output signal of said first combining means is additively combined with said error signal, said subsidiary control loops serving to maintain predetermined absolute values of mean DC voltage levels on said plurality of capacitors.

3. The multilevel convertor as claimed in claim 2, in which said second signal proportional to tap currents is derived by way of sensing means for sensing current flowing in the inductance means, the subsidiary control loops including respective strobing means for enabling the current sensed in the sensing means to be passed on to subsequent circuitry as the second signal proportional to tap currents at those times when the current flowing through the inductance means corresponds to the capacitor tap current associated with the respective capacitor.

10. The multilevel convertor as claimed in claim 3 or claim 9, in which the sensing means is a current transformer.