Apparatus for testing semicondctor wafer
First Claim
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1. An apparatus for testing or burning-in a plurality of semiconductor chips disposed on a wafer, said apparatus comprising:
- a testing substrate;
an active circuit disposed on said testing substrate for activating chips disposed on a wafer to be tested;
a plurality of pads disposed on said testing substrate and positioned so that said pads are disposed in alignment with bonding pads of said chips disposed on said wafer when said testing substrate is engaged to said wafer;
an anisotropic conductive layer disposed on said pads; and
means electrically connected to said testing substrate for testing said wafer, and including a circuit integrated on said testing substrate for rapidly testing a plurality of chips formed on said wafer at the same time and a memory integrated on said testing substrate for storing the results of the test.
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Abstract
The apparatus for collectively burning-in or testing a plurality of semiconductor chips disposed on a wafer without dicing the chips into individuals, the apparatus including a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on the wafer to be tested, a plurality of pads disposed on the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer, and an anisotropic conductive layer disposed on the pads.
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12 Claims
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1. An apparatus for testing or burning-in a plurality of semiconductor chips disposed on a wafer, said apparatus comprising:
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a testing substrate; an active circuit disposed on said testing substrate for activating chips disposed on a wafer to be tested; a plurality of pads disposed on said testing substrate and positioned so that said pads are disposed in alignment with bonding pads of said chips disposed on said wafer when said testing substrate is engaged to said wafer; an anisotropic conductive layer disposed on said pads; and means electrically connected to said testing substrate for testing said wafer, and including a circuit integrated on said testing substrate for rapidly testing a plurality of chips formed on said wafer at the same time and a memory integrated on said testing substrate for storing the results of the test. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification