Receiver circuit with a bus-keeper feature
First Claim
1. A receiver circuit, comprising:
- an input node, for direct connecting to a tristate bus line;
an output node;
an inverter, having an input directly connected to said input node and having an output coupled to said output node;
a first transistor, having a conduction path directly connected on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; and
a second transistor, having a conduction path directly connected on one, side to said input node and coupled on another side to a second bias voltage, and having a control terminal;
wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage;
and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter.
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Accused Products
Abstract
A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.
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Citations
20 Claims
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1. A receiver circuit, comprising:
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an input node, for direct connecting to a tristate bus line; an output node; an inverter, having an input directly connected to said input node and having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one, side to said input node and coupled on another side to a second bias voltage, and having a control terminal; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage; and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An electronic system, comprising:
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a bus line; a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and a receiver, having an output node, comprising; an inverter, having an input directly connected to said bus line and having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal; wherein said first and second bias voltages correspond to said first and second logic states, respectively; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line; and wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit. - View Dependent Claims (8, 9, 10, 13, 14)
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11. An electronic system, comprising:
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a bus line; a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and a receiver, having an output node, comprising; an inverter, having an input directly connected to said bus line ant having an output coupled to said output node; a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal; wherein said first and second bias voltages correspond to said first and second logic states, respectively; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line; wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit; wherein said first and second transistors are field effect transistors; wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter; and
,wherein said driver circuit is of the push-pull type. - View Dependent Claims (12)
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15. A method of controlling a bus line to which a first tristate output driver and a receiver are coupled, comprising:
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first driving said bus line to a selected one of first and second logic levels with said first output driver; after said first driving step, keeping said bus line at the logic level to which it is driven in said driving step by; responsive to said first driving step driving said bus line to said first logic level, turning on a first transistor coupled between said bus line and a first bias voltage corresponding to said first logic level so as to bias said bus line toward said first bias voltage; and responsive to said first driving step driving said bus line to said second logic level, turning on a second transistor coupled between said bus line and a second bias voltage corresponding to said second logic level so as to bias said bus line toward said second bias voltage; placing said first output driver in a high impedance state after said keeping step; after said placing step, maintaining the on state of said first or second transistor turned on in said keeping step; wherein said first and second transistors have significantly weaker drive characteristics than said first output driver. - View Dependent Claims (16, 17, 18)
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19. A receiver circuit, comprising:
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an input node, for coupling to a tristate bus line; a receiver output node; a first inverter, having an input coupled to said input node and having an output coupled to said output node; a first transistor, having a conduction path coupled on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; a second transistor, having a conduction path coupled on one side to said input node and coupled on another side to a second bias voltage, and having a control terminal; a latch comprising a first latch transistor and a second latch transistor, having their source/drain paths connected in series between said first and second bias voltages having their gates coupled in common to said receiver output node, and having their drains coupled to said first inverter; and
,a second inverter having an input coupled to an output of said latch, and an output coupled to said receiver output node; wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage, and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage; and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter. - View Dependent Claims (20)
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Specification