Receiver circuit with a bus-keeper feature

• US 5,532,630 A
• Filed: 07/27/1994
• Issued: 07/02/1996
• Est. Priority Date: 05/06/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Blumberg, Richard J., Kotzur, Gary B., Waggoner, Charles D.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/281,509
• Time in Patent Office: 706 Days
• Field of Search: 307/451, 307/475, 307/571, 307/573, 307/576, 307/473, 307/579, 307/585, 307/270, 307/352, 327/108, 327/112, 327/379, 327/387, 327/389, 327/391, 326/21, 326/24, 326/30, 326/56, 326/57, 326/58, 326/62, 326/86, 326/90, 326/91
• US Class Current: 327/108
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 5/026 with a bidirectional operation

Abstract

A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.

Claims

1. A receiver circuit, comprising:

an input node, for direct connecting to a tristate bus line;

an output node;

an inverter, having an input directly connected to said input node and having an output coupled to said output node;

a first transistor, having a conduction path directly connected on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal; and

a second transistor, having a conduction path directly connected on one, side to said input node and coupled on another side to a second bias voltage, and having a control terminal;

wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage;

and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter.

2. The receiver of claim 1, wherein said first and second transistors are field effect transistors.

3. The receiver of claim 2, wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter.

4. The receiver of claim 3, wherein said inverter comprises first and second inverter transistors of the field effect type, having their source/drain paths connected in series between said first and second bias voltages, having their gates coupled in common to said input node, and having their drains coupled to said output node.

5. The receiver of claim 4, wherein the width/length ratio of said first transistor is significantly smaller than the width/length ratio of said first inverter transistor;

and wherein the width/length ratio of said second transistor is significantly smaller than the width/length ratio of said second inverter transistor.

6. The receiver of claim 4, wherein the source/drain on resistance of said first transistor is significantly greater than that of said first inverter transistor;

and wherein the source/drain on resistance of said second transistor is significantly greater than that of said second inverter transistor.

7. An electronic system, comprising:

a bus line;

a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and

a receiver, having an output node, comprising;

an inverter, having an input directly connected to said bus line and having an output coupled to said output node;

a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and

a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal;

wherein said first and second bias voltages correspond to said first and second logic states, respectively;

wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line;

and wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit.

8. The system of claim 7, wherein said first and second transistors are field effect transistors.

9. The system of claim 8, wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter.

10. The system of claim 9, wherein said inverter comprises first and second inverter transistors of the field effect type, having their source/drain paths connected in series between said first and second bias voltages, having their gates coupled in common to said bus line, and having their drains coupled to said output node;

wherein the source/drain on resistance of said first transistor is significantly greater than that of said first inverter transistor;

and wherein the source/drain on resistance of said second transistor is significantly greater than that of said second inverter transistor.

13. The system of claim 7, wherein said driver circuit and said receiver are disposed on the same integrated circuit.

14. The system of claim 13, wherein said bus line is disposed on the same integrated circuit as said driver circuit and receiver.

11. An electronic system, comprising:

a bus line;

a driver circuit, for selectively driving said bus line to a first logic state or a second logic state, said driver circuit also having a high impedance output state; and

a receiver, having an output node, comprising;

an inverter, having an input directly connected to said bus line ant having an output coupled to said output node;

a first transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a first bias voltage, and having a control terminal; and

a second transistor, having a conduction path directly connected on one side to said bus line and coupled on another side to a second bias voltage, and having a control terminal;

wherein said first and second bias voltages correspond to said first and second logic states, respectively;

wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to said first logic state and said bus line, and in such a manner that said second transistor is on and said first transistor is off responsive to said second logic state at said bus line;

wherein said first and second transistors have drive characteristics which are significantly weaker than said driver circuit;

wherein said first and second transistors are field effect transistors;

wherein said first and second transistors are of first and second conductivity type, respectively, and have their control terminals connected in common to the output of said inverter; and

,

wherein said driver circuit is of the push-pull type.

12. The system of claim 11, wherein said driver circuit comprises:

a pull-up transistor of the field effect type; and

a pull-down transistor of the field effect type;

wherein the width/length ratio of said first transistor is significantly smaller than the width/length ratio of said pull-up transistor;

and wherein the width/length ratio of said second transistor is significantly smaller than the width/length ratio of said pull-down transistor.

15. A method of controlling a bus line to which a first tristate output driver and a receiver are coupled, comprising:

first driving said bus line to a selected one of first and second logic levels with said first output driver;

after said first driving step, keeping said bus line at the logic level to which it is driven in said driving step by;

responsive to said first driving step driving said bus line to said first logic level, turning on a first transistor coupled between said bus line and a first bias voltage corresponding to said first logic level so as to bias said bus line toward said first bias voltage; and

responsive to said first driving step driving said bus line to said second logic level, turning on a second transistor coupled between said bus line and a second bias voltage corresponding to said second logic level so as to bias said bus line toward said second bias voltage;

placing said first output driver in a high impedance state after said keeping step;

after said placing step, maintaining the on state of said first or second transistor turned on in said keeping step;

wherein said first and second transistors have significantly weaker drive characteristics than said first output driver.

16. The method of claim 15, further comprising:

after said maintaining step, driving said bus line to the opposite logic level from that driven in said first driving step.

17. The method of claim 15, wherein said first and second transistors are of the field effect type, and have opposite conductivity type from one another.

18. The method of claim 15, further comprising:

after said maintaining step, driving said bus line with a second output driver coupled thereto, said first output driver remaining in said high impedance state.

19. A receiver circuit, comprising:

an input node, for coupling to a tristate bus line;

a receiver output node;

a first inverter, having an input coupled to said input node and having an output coupled to said output node;

a first transistor, having a conduction path coupled on one side to said input node and coupled on another side to a first bias voltage, and having a control terminal;

a second transistor, having a conduction path coupled on one side to said input node and coupled on another side to a second bias voltage, and having a control terminal;

a latch comprising a first latch transistor and a second latch transistor, having their source/drain paths connected in series between said first and second bias voltages having their gates coupled in common to said receiver output node, and having their drains coupled to said first inverter; and

,

a second inverter having an input coupled to an output of said latch, and an output coupled to said receiver output node;

wherein the control terminals of said first and second transistors are coupled to the output of said inverter in such a manner that said first transistor is on and said second transistor is off responsive to the logic level at said input node corresponding to said first bias voltage, and in such a manner that said second transistor is on and said first transistor is off responsive to the logic level at said input node corresponding to said second bias voltage;

and wherein said first and second transistors have drive characteristics which are significantly weaker than said inverter.

20. The receiver of claim 19, wherein:

the width/length ratio of said first latch transistor is larger than the width length ratio of said first transistor and is smaller than the width/length ratio of said first inverter transistor; and

the width/length ratio of said second latch transistor is larger than the width length ratio of said second transistor and is smaller than the width/length ratio of said second inverter transistor.