Power factor corrected rectifying circuit
First Claim
Patent Images
1. A power factor corrected rectifying circuit comprising:
- a power input port for receiving an AC power source having an input voltage and an input current;
a power output port;
a first rectifying means for providing a first rectified current path between said power input port and said power output port;
a second rectifying means for providing a second rectified current path between said power input port and said power output port, said rectified current paths being capable of simultaneously conducting current;
a current delay means in said first rectified current path for delaying the coupling of current through said first rectified current path such that the waveform of the input current at said power input port approximates the waveform of the input voltage at said power input port; and
a current combining means for coupling the first rectified current path and the second rectified current path to said power output port.
1 Assignment
0 Petitions
Accused Products
Abstract
A power factor corrected rectifying circuit is disclosed. The invention may be implemented using only passive elements and, in such an embodiment, achieves a power factor of about 80%. The invention comprises two rectifying circuits for providing two rectified current paths from an AC input port to an output port. The coupling of current along one of the rectified current paths is delayed. As the sum of the delayed and undelayed currents, the input current pulse is widened to approximate a sinusoid, thereby increasing the power factor.
33 Citations
18 Claims
-
1. A power factor corrected rectifying circuit comprising:
-
a power input port for receiving an AC power source having an input voltage and an input current; a power output port; a first rectifying means for providing a first rectified current path between said power input port and said power output port; a second rectifying means for providing a second rectified current path between said power input port and said power output port, said rectified current paths being capable of simultaneously conducting current; a current delay means in said first rectified current path for delaying the coupling of current through said first rectified current path such that the waveform of the input current at said power input port approximates the waveform of the input voltage at said power input port; and a current combining means for coupling the first rectified current path and the second rectified current path to said power output port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A power factor corrected rectifying circuit comprising:
-
a power input port for receiving an AC power source having an input voltage and an input current; a power output port; a first full-wave rectifier having an input coupled to said power input port and an output directly coupled to said power output port; a second full-wave rectifier having an input coupled to said power input port and an output, said first and second full-wave rectifiers being capable of simultaneously receiving current from said power input port; an inductor having an input coupled to said output of said second full-wave rectifier and an output, said inductor delaying the coupling of current such that the waveform of the input current approximates the waveform of the input voltage; a diode coupled between said output of said inductor and said power output port such that current cannot be conducted from said power output port to said inductor; and a capacitor coupled between said output of said inductor and a fixed reference potential. - View Dependent Claims (12)
-
-
13. A power factor corrected rectifying circuit comprising:
-
a power input port for receiving an AC power source having an input voltage and an input current; a power output port; a first rectifying means for providing a first rectified current path between said power input port and said power output port; a second rectifying means for providing a second rectified current path between said power input port and said power output port, said rectified current paths being capable of simultaneously conducting current; a current delay means in said first rectified current path for delaying the coupling of current through said first rectified current path such that the waveform of the input current at said power input port approximates the waveform of the input voltage at said power input port; a current combining means for coupling the first rectified current path and the second rectified current path to said power output port; and a switching means having a first state wherein current is prevented from coupling through said current delay means and a second state wherein current is permitted to couple through said current delay means. - View Dependent Claims (14, 15, 16, 17, 18)
-
Specification