Soft errors handling in EEPROM devices

• US 5,532,962 A
• Filed: 03/21/1995
• Issued: 07/02/1996
• Est. Priority Date: 05/20/1992
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C., Craig, Jeffrey, Norman, Robert D., Auclair, Daniel L.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/408,109
• Time in Patent Office: 469 Days
• Field of Search: 365/184, 365/185, 365/201, 365/189.07, 365/185.02, 365/185.22, 365/185.24, 365/185.09, 371/21.4, 371/40.2, 371/40.4
• US Class Current: 365/201
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Claims

1. A solid-state memory system comprising:

an array of memory cells that are individually capable of having a threshold voltage programmed or erased to an intended level within a range supported by the memory system;

monitoring means invoked by at least one of the plurality of predefined events of the memory system for identifying one or more cells that individually have a threshold voltage shifted beyond a predetermined margin from said intended level; and

writing means for re-writing said shifted threshold voltage back to said intended level;

wherein said plurality of predefined events of the memory system including memory operations on a portion of the memory array that are liable to preturb cells in other portions of the memory array outside of said portion; and

wherein said monitoring means samples one of a plurality of fractions of the memory array outside of said portion, such that statistically substantially all said plurality of factions of the memory array get monitored after at most a predetermined number of said sampling.

2. A solid-state memory system as in claim 1, wherein said memory operations include programming operations.

3. A solid-state memory system as in claim 1, wherein said memory operations include programming and erasing operations.

4. A solid-state memory system as in claim 1, wherein said memory operations include read operations.

5. A solid-state memory system as in claim 1, wherein said predetermined number of said sampling is greater than two.

6. A solid-state memory system comprising:

an array of memory cells, each cell capable of having at least one of its threshold voltages programmed or erased to an intended level within a range supported by the memory system;

monitoring means invoked at at least one of a plurality of predefined events of the memory system for identifying one or more cells each having a threshold voltage shifted beyond a predetermined margin from its intended level; and

writing means for re-writing said shifted threshold voltage back to its intended level; and

wherein said plurality of predefined events of the memory system are memory operations on a portion of the memory array that are liable to perturb cells within said portion of the memory array.

7. A solid-state memory system as in claim 6, wherein said memory operations include read operations.

8. A solid-state memory system comprising:

an array of memory cells, each cell capable of having at least one of its threshold voltages programmed or erased to an intended level within a range supported by the memory system;

monitoring means invoked at at least one of a plurality of predefined events of the memory system for identifying one or more cells each having a threshold voltage shifted beyond a predetermined margin from its intended level; and

writing means for re-writing said shifted threshold voltage back to its intended level; and

wherein;

said memory array is partitioned into a plurality of sectors, each sector having cells that are all at a time subjected to one of said specific regular memory operations; and

said monitoring means samples a predetermined number of sectors during each invocation, such that statistically each sector in the memory array gets monitored after at most a predetermined number of said plurality of predefined events.

9. A solid-state memory system as in claim 8, wherein said plurality of predefined events of the memory system are memory operations on a portion of the memory array that are liable to perturb cells in other portions of the memory array.

10. A solid-state memory system as in claim 9, wherein said memory operations include programming operations.

11. A solid-state memory system as in claim 9, wherein said memory operations include programming and erasing operations.

12. A solid-state memory system as in claim 9, wherein said memory operations include read operations.

13. A solid-state memory system as in claim 8, wherein said plurality Of predefined events of the memory system are memory operations on a portion of the memory array that are liable to perturb cells within said portion of the memory array.

14. A solid-state memory system as in claim 13, wherein said memory operations include read operations.

15. In a solid-state memory system including an array of memory cells that are individually capable of having a threshold voltage programmed or erased to an intended level within a range supported by the memory system, wherein soft errors may arise from cells with a shifted threshold voltage, a method for detecting and correcting soft errors comprising the steps of:

monitoring at at least one of a plurality of predefined events of the memory system to identify one or more cells each that individually have a threshold voltage shifted beyond a predetermined margin from said intended level; and

re-writing said shifted threshold voltage back to said intended level;

wherein

said plurality of predefined events of the memory system include memory operations on a portion of the memory array that are liable to perturb cells in other portions of the memory array outside of said portion; and

said monitoring samples one of a plurality of fractions of the memory array outside of said portion, such that statistically substantially all of said plurality of fractions of the memory array get monitored after at most a predetermined number of said sampling.

16. A method for detecting and correcting soft errors in solid-state memory system as in claim 15, wherein said memory operations include programming operations.

17. A method for detecting and correcting soft errors in solid-state memory system as in claim 15, wherein said memory operations include programming and erasing operations.

18. A method for detecting and correcting soft errors in a solid-state memory system as in claim 15, wherein said memory operations include read operations.

19. A method for detecting and correcting soft errors in solid-state memory as in claim 15, wherein said predetermined number of said sampling is greater than two.

20. In a solid-state memory system including an array of memory cells, each cell capable of having at least one of its threshold voltages programmed or erased to an intended level within a range supported by the memory system, wherein soft errors may arise from cells with a shifted threshold voltage, a method for detecting and correcting soft errors comprising the steps of:

monitoring at at least one of a plurality of predefined events of the memory system to identify one or more cells each having a threshold voltage shifted beyond a predetermined margin from its intended level; and

re-writing said shifted threshold voltage back to its intended level;

wherein said plurality of predefine events of the memory system are memory operations on a portion of the memory array that are liable to perturb cells within said portion of the memory array.

21. A method for detecting and correcting soft errors in a solid-state memory system as in claim 20, wherein said memory operations include read operations.

22. In a solid-state memory system including an array of memory cells, each cell capable of having at least one of its threshold voltages programmed or erased to an intended level within a range supported by the memory system, wherein soft errors may arise from cells with a shifted threshold voltage, a method for detecting and correcting soft errors comprising the steps of:

monitoring at at least on of plurality of predefined events of the memory system to identify one or more cells each having a threshold voltage shifted beyond a predetermined margin from its intended level; and

re-writing said shifted threshold voltage back to its intended level;

wherein;

said memory array is partitioned into a plurality of sectors, each sectors having cells that are all at a time subjected to one of said specific regular memory operations; and

said monitoring means samples a predetermined number of sectors during each invocation, such that statistically each sector in the memory array gets monitored after at most a predetermined number of said plurality of predefined events.

23. A method for detecting and correcting soft errors in solid-state memory system as in claim 22, wherein said plurality of predefined events of the memory system are memory operations on a portion of the memory array that are liable to perturb cells in other portions of the memory array.

24. A method for detecting and correcting soft errors in solid-state memory system as in claim 23, wherein said memory operations include programming operations.

25. A method for detecting and correcting soft errors in solid-state memory system as in claim 23, wherein said memory operations include programming and erasing operations.

26. A method for detecting and correcting soft errors in a solid-state memory system as in claim 23, wherein said memory operations include read operations.

27. A method for detecting and correcting soft errors in a solid-state memory system as in claim 22, wherein said plurality of predefined events of the memory system are memory operations on a portion of the memory array that are liable to perturb cells within said portion of the memory array.

28. A method for detecting and correcting soft errors in a solid-state memory system as in claim 27, wherein said memory operations include read operations.

29. A solid-state memory system comprising:

an array of memory cells that are individually capable of having a threshold voltage programmed or erased to an intended level within a range supported by the memory system;

monitoring means invoked by at least one of a plurality of predefined events of the memory system for identifying one or more cells that individually have a threshold voltage shifted beyond a predetermined margin from said intended level; and

writing means for re-writing said shifted threshold voltage back to said intended level;

wherein said plurality of predefined events of the memory system include memory operations on a portion of the memory array that are liable to perturb cells of the memory array outside of said portion; and

wherein said monitoring means includes identification by error correction code of said one or more cells that individually have said shifted threshold voltage.

30. A solid-state memory system as in claim 29, wherein said portion of the memory array includes a sector of cells that are all erasable as a group.

31. In a solid-state memory system including an array of memory cells that are individually capable of having a threshold voltage programmed or erased to an intended level within a range supported by the memory system, wherein soft errors may arise from cells with a shifted threshold voltage, a method for detecting and correcting soft errors comprising:

monitoring at at least one of a plurality of predefined events of the memory system to identify one or more cells that individually have a threshold voltage shifted beyond a predetermined margin from said intended level; and

re-writing said shifted threshold voltage back to said intended level;

wherein said predefined events of the memory system include memory operations on a portion of the memory array that are liable to perturb cells in other portions of the memory array outside of said portion; and

wherein said monitoring includes identifying by error correction code said one or more cells that individually have said shifted threshold voltage.

32. A method for detecting and correcting soft errors in a solid-state memory system as in claim 31, wherein said portion of the memory array includes a sector of cells that are all erasable as a group.