×

Soft errors handling in EEPROM devices

  • US 5,532,962 A
  • Filed: 03/21/1995
  • Issued: 07/02/1996
  • Est. Priority Date: 05/20/1992
  • Status: Expired due to Term
First Claim
Patent Images

1. A solid-state memory system comprising:

  • an array of memory cells that are individually capable of having a threshold voltage programmed or erased to an intended level within a range supported by the memory system;

    monitoring means invoked by at least one of the plurality of predefined events of the memory system for identifying one or more cells that individually have a threshold voltage shifted beyond a predetermined margin from said intended level; and

    writing means for re-writing said shifted threshold voltage back to said intended level;

    wherein said plurality of predefined events of the memory system including memory operations on a portion of the memory array that are liable to preturb cells in other portions of the memory array outside of said portion; and

    wherein said monitoring means samples one of a plurality of fractions of the memory array outside of said portion, such that statistically substantially all said plurality of factions of the memory array get monitored after at most a predetermined number of said sampling.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×