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Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells

  • US 5,532,964 A
  • Filed: 05/04/1995
  • Issued: 07/02/1996
  • Est. Priority Date: 07/08/1993
  • Status: Expired due to Term
First Claim
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1. An EEPROM having a plurality of memory cells respectively connected to a plurality of bit lines, and a bit line selection circuit including a plurality of switches having a plurality of control inputs connected to a plurality of bit line selection signals, a plurality of outputs connected to said plurality of bit lines, and a sense line input connected through said plurality of switches to a selected one of said plurality of bit lines by respectively turning on or off each of said plurality of switches as determined by said plurality of bit line selection signals, said EEPROM further including a voltage regulator circuit comprising:

  • a n-mos transistor having a drain electrode connected to a voltage supply, a source electrode connected to said sense line input of said selection circuit, and a control gate; and

    a differential amplifier having a first input connected to a reference voltage, a second input directly connected to said selected one of said plurality of bit lines, and an output, proportional to a difference between said first and second inputs, connected to said control gate of said n-mos transistor so that a bit line voltage on said selected one of said plurality of bit lines is maintained to be equal to said reference voltage.

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