Multi-protocol packet framing over an isochronous network

• US 5,533,018 A
• Filed: 12/21/1994
• Issued: 07/02/1996
• Est. Priority Date: 12/21/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Swenson, Erik R., DeJager, Gregory L.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/361,603
• Time in Patent Office: 559 Days
• Field of Search: 370/60, 370/60.1, 370/79, 370/85.1, 370/85.2, 370/85.3, 370/94.1, 370/94.2
• US Class Current: 370/395.5
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.

Claims

1. An integrated circuit, comprising:

an isochronous network port;

a first protocol packet framer/deframer circuit;

a second protocol packet framer/deframer circuit; and

a circuit switch multiplexer/demultiplexer coupled to said isochronous network port, said first protocol packet framer/deframer circuit, and said second protocol packet framer/deframer circuit, wherein said circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer, and a storage device, said multiplexer/demultiplexer being at least in part controlled based on a value output from said storage device.

2. The integrated circuit of claim 1, wherein a plurality of isochronous frames are received on said isochronous network port, each of said isochronous frames comprising a plurality of slots, a first of said slots of a frame being supplied to and deframed by said first protocol packet framer/deframer circuit, a second of said slots of said frame being supplied to and deframed by said second protocol packet framer/deframer circuit.

3. The integrated circuit of claim 1, wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots.

4. The integrated circuit of claim 3, wherein said first protocol packet framer/deframer circuit deframes ATM cells.

5. The integrated circuit of claim 3, wherein said first protocol packet framer/deframer circuit deframes both ATM cells and ATM packets.

6. The integrated circuit of claim 1, wherein said storage device comprises a plurality of memory locations, and wherein said circuit switch multiplexer/demultiplexer further comprises:

a receive counter, said receive counter being incremented after a receipt of a slot of information received on said isochronous network port, a count value output from said receive counter pointing to a corresponding memory location of said plurality of memory locations of said storage device.

7. The integrated circuit of claim 1, further comprising:

a parallel bus port, said storage device being accessible from said parallel bus port.

8. The integrated circuit of claim 1, further comprising:

a parallel bus port;

parallel bus interface circuitry coupled to said parallel bus port;

a memory; and

an arbiter circuit coupled to said parallel bus interface circuitry and to said memory, said arbiter arbitrating access to said memory.

9. The integrated circuit of claim 8, further comprising:

a buffer manager circuit coupled to said first protocol packet framer/deframer circuit, said second protocol packet framer/deframer circuit and to said arbiter circuit, said buffer manager circuit comprising;

first and second receive pointer registers for pointing to a receive buffer in said memory; and

first and second transmit pointer registers for pointing to a transmit buffer in said memory.

10. The integrated circuit of claim 8, further comprising:

means, coupled to said circuit switch multiplexer/demultiplexer, for managing buffering of substantially nondeframed isochronous network data in said memory.

11. A method, comprising:

deframing information of a slot of a frame of network information using a first protocol packet deframer circuit;

deframing information of another slot of said frame of network information using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits both being disposed on the same integrated circuit;

incrementing a counter of said integrated circuit so that a count value output from said counter corresponds with a slot number of the slot being received into said integrated circuit; and

using said count value to address a slot mapping memory of said integrated circuit.

12. The method of claim 11, wherein said integrated circuit has a parallel bus port, said method further comprising:

programming said slot mapping memory of said integrated circuit via said parallel bus port.

13. The method of claim 11, further comprising:

storing information deframed by said first protocol packet deframer circuit in a first ring buffer; and

storing information deframed by said second protocol packet deframer circuit in a second ring buffer.

14. An integrated circuit, comprising:

a first packet deframer circuit which deframes information in accordance with a first network protocol;

a second packet deframer circuit which deframes information in accordance with a second network protocol; and

means for causing said first packet deframer circuit to deframe information in a first isochronous network slot of a frame in accordance with said first network protocol and for causing said second packet deframer circuit to deframe information in a second isochronous network slot of said frame in accordance with said second network protocol, wherein said means comprises means for storing slot mapping information.

15. The integrated circuit of claim 14, wherein said first network protocol is an ATM protocol and wherein said second network protocol is an HDLC protocol.

17. The integrated circuit of claim 14, further comprising:

a first packet framer circuit which frames information in accordance with a network protocol; and

a second packet framer circuit which frames information in accordance with a network protocol,

wherein said means for causing comprises;

a multiplexer having a first input lead, a second input lead, and an output lead, said first input lead being coupled to an output lead of said first packet framer circuit, said second input lead being coupled to an output lead of said second packet framer circuit, and an output lead being coupled to an output part of an isochronous network port of said integrated circuit; and

a demultiplexer having an input lead, a first output lead, and a second output lead, said input lead being coupled to an input part of said isochronous network port, said first output lead being coupled to an input lead of said first packet deframer circuit, and said second output lead being coupled to an input lead of said second packet deframer circuit.

16. An integrated circuit comprising:

a first packet deframer circuit which deframes information in accordance with a first network protocol;

a second packet deframer circuit which deframes information in accordance with a second network protocol;

means for causing said first packet deframer circuit to deframe information in a first isochronous network slot of a frame in accordance with said first network protocol and for causing said second packet deframer circuit to deframe information in a second isochronous network slot of said frame in accordance with said second network protocol;

means for managing a receive ring buffer;

a parallel bus port; and

parallel bus interface circuitry coupled to said parallel bus port.

18. An integrated circuit, comprising:

an isochronous network port, wherein the isochronous network port receives frame of information, said frame having a plurality of non-isochronous and isochronous slots, and each of said isochronous slots having information of one of at least a first protocol or a second protocol;

a first protocol packet framer/deframer circuit;

a second protocol packet framer/deframer circuit; and

a circuit switch multiplexer/demultiplexer coupled to said isochronous network port, said first protocol packet framer/deframer circuit, and said second protocol packet framer/deframer circuit, wherein the circuit switch multiplexer/demultiplexer couples said isochronous first protocol slots to the first protocol packet framer/deframer circuit and couples said isochronous second protocol slots to the second protocol packet framer/deframer circuit.

19. The integrated circuit of claim 18 further comprising:

a first demultiplexer coupled to said isochronous network port, wherein the first demultiplexer separates the non-isochronous slots from the isochronous slots, and the circuit switch multiplexer/demultiplexer is coupled to the first demultiplexer.

20. The integrated circuit of claim 18, wherein said circuit switch multiplexer/demultiplexer comprises:

a multiplexer/demultiplexer; and

a storage device, said multiplexer/demultiplexer being at least in part controlled based on a value output from said storage device.

21. The integrated circuit of claim 18, wherein a plurality of isochronous slots are received on said isochronous network port, a first of said isochronous slots of a frame being provided to and deframed by said first protocol packet framer/deframer circuit, and a second of said isochronous slots of said frame being provided to and deframed by said second protocol packet framer/deframer circuit.

22. The integrated circuit of claim 18, wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots.

23. The integrated circuit of claim 22, wherein said first protocol packet framer/deframer circuit deframes ATM cells.

24. The integrated circuit of claim 22, wherein said first protocol packet framer/deframer circuit deframes both ATM cells and ATM packets.

25. The integrated circuit of claim 20, wherein said storage device comprises a plurality of memory locations, and wherein said circuit switch multiplexer/demultiplexer further comprises:

a receive counter, said receive counter being incremented after a receipt of a slot of information received on said isochronous network port, a count value output from said receive counter pointing to a corresponding memory location of said plurality of memory locations of said storage device.

26. The integrated circuit of claim 20, further comprising:

a parallel bus port, said storage device being accessible from said parallel bus port.

27. The integrated circuit of claim 20, further comprising:

a parallel bus port;

parallel bus interface circuitry coupled to said parallel bus port;

a memory; and

an arbiter circuit coupled to said parallel bus interface circuitry and to said memory, said arbiter arbitrating access to said memory.

28. The integrated circuit of claim 27, further comprising:

a buffer manager circuit coupled to said first protocol packet framer/deframer circuit, said second protocol packet framer/deframer circuit and to said arbiter circuit, said buffer manager circuit comprising;

first and second receive pointer registers for pointing to a receive buffer in said memory; and

first and second transmit pointer registers for pointing to a transmit buffer in said memory.

29. The integrated circuit of claim 27, further comprising:

means, coupled to said circuit switch multiplexer/demultiplexer, for managing buffering of substantially nondeframed isochronous network data in said memory.

30. A method, comprising:

framing network information, wherein network information frames include non-isochronous and isochronous slots;

deframing information of an isochronous slot of using a first protocol packet deframer circuit; and

deframing information of another isochronous slot using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits both being disposed on the same integrated circuit.

31. The integrated circuit of claim 30, wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots.

32. The method of claim 30 wherein each isochronous slot is formatted with at least one of a first protocol or a second protocol, the method further comprising the steps of:

separating the non-isochronous slots from the isochronous slots into a non-isochronous data stream and an isochronous data stream;

coupling the isochronous slots formatted with the first protocol to the first protocol packet deframer circuit; and

coupling the isochronous slots formatted with the second protocol to the second protocol packet deframer circuit.

33. The method of claim 32 further comprising the step of:

demultiplexing the isochronous slots; and

wherein the separating step includes the step of demultiplexing with a first demultiplexer each network information frame.

34. The method of claim 30 further comprising the steps of:

flaming information having a first protocol using a first protocol packet framer circuit;

framing information having a second protocol using a second protocol packet framer circuit;

combining the first protocol framed information and the second protocol framed information into isochronous slots; and

combining isochronous slots with non-isochronous slots into a frame.

35. The method of claim 30, further comprising:

incrementing a counter of said integrated circuit so that a count value output from said counter corresponds with a slot number of the slot being received into said integrated circuit; and

using said count value to address a slot mapping memory of said integrated circuit.

36. The method of claim 35, wherein said integrated circuit has a parallel bus port, said method further comprising:

programming said slot mapping memory of said integrated circuit via said parallel bus port.

37. The method of claim 35, further comprising:

storing information deframed by said first protocol packet deframer circuit in a first ring buffer; and

storing information deframed by said second protocol packet deframer circuit in a second ring buffer.

38. An integrated circuit, comprising:

means for framing information, each information frame having isochronous and non-isochronous slots and each of said isochronous slots having information formatted by one of at least a first network protocol or a second network protocol;

means for receiving the framed information;

means for separating the isochronous slots and the non-isochronous slots;

a first means for combining information formatted by a first protocol into a first packet;

a second means for combining information formatted by a second protocol into a second packet; and

means for coupling first protocol formatted information in an isochronous slot to the first means for combining and for coupling second protocol formatted information in another isochronous slot to the second means for combining.

39. The integrated circuit of claim 38 further comprising:

a first means for separating a packet of information formatted by a first protocol into first segments of information;

a second means for disassembling a packet of information formatted by a second protocol into second segments of information; and

means for combining the first information segments and the second information segments into an isochronous data stream;

means for combining the isochronous data stream with a non-isochronous data stream.

40. The integrated circuit as in claim 39 wherein the means for combining includes the step of inserting the first segments and the second segments into isochronous slots of a frame and non-isochronous data stream segments into non-isochronous slots of the frame.

41. The integrated circuit of claim 38, wherein said first network protocol is an ATM protocol and wherein said second network protocol is an HDLC protocol.

42. The integrated circuit of claim 38, wherein said means for coupling comprises means for storing slot mapping information.

43. The integrated circuit of claim 38, further comprising:

means for managing a receive ring buffer;

a parallel bus port; and

parallel bus interface circuitry coupled to said parallel bus port.

44. The integrated circuit of claim 38, further comprising:

a first packet framer circuit which frames information in accordance with a network protocol; and

a second packet framer circuit which frames information in accordance with a network protocol,

wherein said means for coupling comprises;

a multiplexer having a first input lead, a second input lead, and an output lead, said first input lead being coupled to an output lead of said first packet framer circuit, said second input lead being coupled to an output lead of said second packet framer circuit, and an output lead being coupled to an output part of an isochronous network port of said integrated circuit; and

a demultiplexer having an input lead, a first output lead, and a second output lead, said input lead being coupled to an input part of said isochronous network port, said first output lead being coupled to an input lead of said first packet deframer circuit, and said second output lead being coupled to an input lead of said second packet deframer circuit.