Low frequency common mode rejection in a clock circuit

• US 5,533,053 A
• Filed: 05/16/1994
• Issued: 07/02/1996
• Est. Priority Date: 05/16/1994
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Inventors: Hershbarger, Russell A.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/243,563
• Time in Patent Office: 778 Days
• Field of Search: 375/219, 375/257, 375/316-318, 375/377, 333/12, 333/32-33, 333/24 C, 340/310.05, 340/310.06
• US Class Current: 375/257
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

A method and apparatus for passing a high frequency signal across an isolation barrier while rejecting low frequency common mode interference is provided. A high frequency signal is coupled across an isolation barrier. A circuit comprising an element having an impedance that is a function of frequency rejects low frequency common mode interference. The high frequency signal is provided as an output. The present invention is useful, for example, for isolating telephone apparatus, such as a telephone modem, from a telephone line.

Claims

1. Apparatus comprising:

a driver for providing a signal;

a capacitor having a first terminal and a second terminal, said first terminal coupled to said driver, said capacitor for coupling said signal from said first terminal to said second terminal;

an impedance element comprising a transconductance element coupled to said second terminal for filtering said signal, wherein said impedance element has a highpass filter characteristic and wherein said impedance element further comprises a feedback capacitor in a feedback loop around said transconductance element;

a comparator coupled to said impedance element for comparing said signal; and

a reference voltage source coupled to said impedance element and to said comparator, wherein said transconductance element comprises;

an amplifier having a first amplifier input, a second amplifier input, and an amplifier output;

a field effect transistor (FET) having a gate terminal, a first FET terminal, and a second FET terminal, said amplifier output coupled to said gate terminal, said first amplifier input coupled to said first FET terminal, said second FET terminal coupled to a first feedback capacitor terminal of said feedback capacitor, and said second amplifier input coupled to a second feedback capacitor terminal of said feedback capacitor.

2. The apparatus of claim 1 wherein said reference voltage source is coupled to said first amplifier input.

3. The apparatus of claim 2 wherein said capacitor couples said signal across an isolation barrier.

4. The apparatus of claim 3 wherein said isolation barrier isolates a modem circuit from a telephone line.

5. The apparatus of claim 4 wherein said impedance element rejects low frequency common mode signals.

6. The apparatus of claim 5 wherein said signal is a clock signal.