Multi-level data transmitter

• US 5,533,054 A
• Filed: 07/09/1993
• Issued: 07/02/1996
• Est. Priority Date: 07/09/1993
• Status: Expired due to Fees

• Current Assignee: Pulse Electronics Corporation (Yageo Corporation)
• Original Assignee: Technitrol Incorporated
• Inventors: Conroy, Keith M., DeAndrea, John J.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/089,973
• Time in Patent Office: 1,089 Days
• Field of Search: 375/286-288, 375/293, 375/318, 375/333, 375/359-361, 375/219, 375/257-258, 333/177, 333/180, 326/60, 327/331, 327/333, 341/56-57, 341/70-71
• US Class Current: 375/286
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes

Abstract

A data transmitter circuit includes a pseudoternary conversion circuit for converting a binary logic signal to a differential pseudoternary signal having symmetric rise and fall characteristics. The output of the pseudoternary conversion circuit is filtered and passed to an electrically conductive medium via an isolation transformer. The conversion circuit includes a symmetric arrangement of toggle circuits which respond to transitions in respective complementary binary signals constituting a differential binary input signal. Voltage dividers are connected to the output terminals of the toggle circuits for providing three levels of output voltages in response to the logical states of the toggle circuits.

Claims

1. A conversion circuit for converting a differential binary signal to a three-level signal, the differential binary signal including a first binary signal and a complementary of the first binary signal, said conversion circuit comprising:

(a) a first latch having a first latching input, a first triggering input, a first non-inverting output, and a first inverting output;

said first triggering input connected to receive said first binary signal, and said first latching input connected to receive said first inverting output, whereby said first inverting output is latched at said first latching input in response to a transition in said first binary signal;

(b) a second latch having a second latching input, a second triggering input, a second non-inverting output, and a second inverting output;

said second triggering input connected to receive said complementary of the first binary signal, and said second latching input connected to receive said second inverting output, whereby said second inverting output is latched at said second latching input in response to a transition in said complementary of the first binary signal;

(c) a first voltage divider connected between the respective first and second non-inverting outputs for providing a first voltage level when the first and second non-inverting outputs are logical high, a second voltage level when first and second non-inverting outputs are logical low, and a third, intermediate, voltage level when said first and second non-inverting outputs are in opposite logical conditions, whereby said three-level signal is provided.

2. The conversion circuit of claims 1 further comprising a second voltage divider connected between the first and second inverting outputs for providing a fourth voltage level when both first and second inverting outputs are logical high, a fifth voltage level when both first and second inverting outputs are not logical low, and a sixth, intermediate, voltage level when said first and second inverting outputs are in opposite logical conditions, whereby the three-level signal is provided by said conversion circuit as a differential signal according to the voltage differences between the first and second voltage dividers.

3. The conversion circuit of claim 1 wherein the first and second latches are formed to be responsive to transitions of the respective first binary signal and the complementary of the first binary signal which occur in a positive direction of polarity.