Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applications
First Claim
1. A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation, comprising the steps of:
- providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors are to be formed;
doping the polycrystalline layer left exposed by said first mask;
providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and
N+ implanting the active areas of the N-channel transistors.
2 Assignments
0 Petitions
Accused Products
Abstract
A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,
providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,
doping the polycrystalline layer uncovered by said first mask,--providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, and
N+ implanting the active areas of the N-channel transistors.
14 Citations
14 Claims
-
1. A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation, comprising the steps of:
-
providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors are to be formed; doping the polycrystalline layer left exposed by said first mask; providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and N+ implanting the active areas of the N-channel transistors. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-well, comprising the steps of:
-
providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors having a first threshold voltage are to be formed; doping the polycrystalline layer uncovered by said first mask providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and N+ implanting the active areas of the N-channel transistors. - View Dependent Claims (8, 9, 10)
-
-
11. A process for forming P-channel MOS transistors with different threshold voltages in semiconductor integrated circuits having a layer of polycrystalline silicon using CMOS processes, said P-Channel MOS transistors comprising first threshold voltage P-channel MOS transistors, said circuits comprising N-channel MOS transistors, the process comprising the steps of:
-
providing a first mask over said semiconductor regions where said first threshold voltage P-channel MOS transistors are to be formed; doping the polycrystalline layer left exposed by said first mask; providing a second mask for protecting said semiconductor regions where said P-channel MOS transistors are to be formed; N+ implanting active areas of said N-channel MOS transistors; and P+ implanting active areas of said P-channel MOS transistors. - View Dependent Claims (12)
-
-
13. A process for forming P-channel MOS transistors in semiconductor integrated circuits for analog applications using CMOS processes, the P-channel MOS transistors including first threshold voltage P-channel MOS transistors and second threshold voltage P-channel MOS transistors, the semiconductor integrated circuits having resistors and N-channel MOS transistors, the process comprising the steps of:
-
providing a substrate of P-type semiconductor material; providing a plurality of N-wells in the substrate; providing a layer of polycrystalline silicon; depositing a first layer of silicon oxide to provide a first mask over the resistors and the N-well semiconductor regions where the first threshold voltage P-channel transistors are to be formed; doping the polycrystalline layer left exposed by the first mask to form gate terminals of the N-channel transistors and the second threshold voltage P-channel transistors, the-second threshold voltage being higher than the first threshold voltage; removing the first mask upon completion of said doping step; depositing a second layer of silicon oxide to provide a second mask over the resistors and the N-well semiconductor regions where the first threshold voltage P-channel transistors and the second threshold voltage P-channel transistors are to be formed; N+ implanting active areas of the N-channel transistors; removing the second mask upon completion of said N+ implanting step; depositing a third layer of silicon oxide to provide a third mask over the resistors and the N-channel transistors; and P+ implanting active areas of the first threshold voltage P-channel transistors and the second threshold voltage P-channel transistors. - View Dependent Claims (14)
-
Specification