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Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applications

  • US 5,534,448 A
  • Filed: 07/28/1994
  • Issued: 07/09/1996
  • Est. Priority Date: 07/29/1993
  • Status: Expired due to Term
First Claim
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1. A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation, comprising the steps of:

  • providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors are to be formed;

    doping the polycrystalline layer left exposed by said first mask;

    providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and

    N+ implanting the active areas of the N-channel transistors.

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