Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with sidewall spacers
First Claim
1. A method of constructing a plurality of memory cells across a surface of a semiconductor substrate, comprising the steps of:
- forming a plurality of parallel elongated strips of field oxide with walls substantially perpendicular to said substrate surface, said field oxide strips being elongated in a first direction along said substrate surface and spaced apart in a second direction to form openings therebetween, said first and second directions being substantially orthogonal with each other,forming a first plurality of parallel elongated strips of polysilicon over said field oxide strips and extending into said openings, said first plurality of polysilicon strips being elongated in said second direction and spaced apart in said first direction, thereby exposing portions of the field oxide strips and openings which lie between the polysilicon strips,removing by a dry etch process at least a portion of the field oxide strips that are exposed between the first polysilicon strips, andimplanting ions into the surface of the substrate in regions positioned between the first polysilicon strips including locations where the field oxide strips extending therebetween have been removed, said implanted regions being elongated in the second direction.
3 Assignments
0 Petitions
Accused Products
Abstract
Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.
-
Citations
9 Claims
-
1. A method of constructing a plurality of memory cells across a surface of a semiconductor substrate, comprising the steps of:
-
forming a plurality of parallel elongated strips of field oxide with walls substantially perpendicular to said substrate surface, said field oxide strips being elongated in a first direction along said substrate surface and spaced apart in a second direction to form openings therebetween, said first and second directions being substantially orthogonal with each other, forming a first plurality of parallel elongated strips of polysilicon over said field oxide strips and extending into said openings, said first plurality of polysilicon strips being elongated in said second direction and spaced apart in said first direction, thereby exposing portions of the field oxide strips and openings which lie between the polysilicon strips, removing by a dry etch process at least a portion of the field oxide strips that are exposed between the first polysilicon strips, and implanting ions into the surface of the substrate in regions positioned between the first polysilicon strips including locations where the field oxide strips extending therebetween have been removed, said implanted regions being elongated in the second direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification