Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with sidewall spacers

• US 5,534,456 A
• Filed: 03/30/1995
• Issued: 07/09/1996
• Est. Priority Date: 05/25/1994
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Chien, Henry, Yuan, Jack H., Samachisa, Gheorghe
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/414,333
• Time in Patent Office: 467 Days
• Field of Search: 437/43, 437/48, 437/52, 257/316
• US Class Current: 438/263
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: Y10S 438/917 Deep level dopants, e.g. gold, chromium, iron or nickel
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

Claims

1. A method of constructing a plurality of memory cells across a surface of a semiconductor substrate, comprising the steps of:

forming a plurality of parallel elongated strips of field oxide with walls substantially perpendicular to said substrate surface, said field oxide strips being elongated in a first direction along said substrate surface and spaced apart in a second direction to form openings therebetween, said first and second directions being substantially orthogonal with each other,

forming a first plurality of parallel elongated strips of polysilicon over said field oxide strips and extending into said openings, said first plurality of polysilicon strips being elongated in said second direction and spaced apart in said first direction, thereby exposing portions of the field oxide strips and openings which lie between the polysilicon strips,

removing by a dry etch process at least a portion of the field oxide strips that are exposed between the first polysilicon strips, and

implanting ions into the surface of the substrate in regions positioned between the first polysilicon strips including locations where the field oxide strips extending therebetween have been removed, said implanted regions being elongated in the second direction.

2. The method according to claim 1, comprising the additional steps of:

depositing a dielectric in the openings between the field oxide strips and in the spaces between the first polysilicon strips, said dielectric being deposited to extend above and over top surfaces of said first polysilicon strips,

removing said dielectric to a level below the top surfaces of the first plurality of polysilicon strips,

forming a second plurality of strips of polysilicon extending over said first polysilicon strips, said second polysilicon strips being elongated in said first direction and spaced apart in said second direction, and

etching through said first polysilicon strips in spaces between the second polysilicon strips, thereby to separate the first polysilicon strips into individual memory cell floating gates.

3. The method according to claim 2, wherein the step of forming a second plurality of polysilicon strips includes the steps of:

depositing a continuous layer of polysilicon,

forming a plurality of parallel elongated strips of a dielectric material over said polysilicon layer in a manner providing vertical sidewalls extending therefrom, said dielectric material strips being elongated in said first direction and spaced apart in said second direction,

forming spacers along said dielectric strip vertical sidewalls, thereby to decrease a dimension of spaces between the dielectric strips, and

etching away the polysilicon material layer through the spaces between the dielectric strips, whereby the resulting space between the second plurality of polysilicon strips may be made less than that which can be obtained within existing photolithography resolution limits.

4. The method according to claim 3, comprising the additional steps of:

forming a dielectric layer across edges of the second polysilicon strips facing spaces therebetween without occluding said spaces, thereby leaving openings therebetween,

etching the first plurality of strips of polysilicon through said openings, thereby exposing surfaces of the first plurality of strips of polysilicon,

growing an oxide layer on said exposed surfaces, and

forming a third plurality of elongated parallel polysilicon strips across said strips of dielectric material and filling at least some of the resulting space between the second plurality of polysilicon strips, said third plurality of polysilicon strips being elongated in said first direction and spaced apart in said second direction.

5. The method according to claim 1, wherein the step of forming the elongated strips of field oxide includes doing so directly on the substrate surface, and further comprising thereafter but before forming the first plurality of elongated strips of polysilicon material, the additional steps of:

forming oxide spacers along the sidewalls of the field oxide openings, thereby to narrow a space therebetween without eliminating said space, and

forming a gate oxide layer on the substrate surface in such space between the field oxide strips and their spacers.

6. The method according to claim 1 wherein the step of forming the field oxide strips includes doing so by forming a continuous layer of field oxide, and then etching openings through said continuous oxide layer by a dry etch process.

7. The method according to claim 3 wherein the step of forming the dielectric strips includes doing so by forming a continuous layer of oxide, and then etching openings through said continuous oxide layer by a dry etch process.

8. The method according to claim 3 wherein the step of forming the second plurality of polysilicon strips includes doing so with spaces therebetween being positioned over the field oxide strips, and wherein the step of etching through the first polysilicon strips includes doing so over the field oxide strips.

9. The method according to claim 1 wherein the step of forming the first plurality of strips of polysilicon includes the steps of:

depositing a sufficient amount of polysilicon material on said field oxide strips and extending into said trenches so that a resulting top surface is substantially smooth,

oxidizing the polysilicon material to a substantially uniform depth across said top surface,

stripping away the oxidized polysilicon material, thereby to leave a polysilicon layer with a substantially smooth surface, and

separating the polysilicon layer into said first plurality of elongated strips of polysilicon.