Integrated circuit bare chip carrier

• US 5,534,785 A
• Filed: 06/27/1995
• Issued: 07/09/1996
• Est. Priority Date: 10/20/1992
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Yoshizaki, Tsutomu, Maruyama, Shigeyuki, Ohno, Tsuyoshi
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US08/495,149
• Time in Patent Office: 378 Days
• Field of Search: 324/758, 324/754, 324/755, 324/761, 324/762
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433

Abstract

An IC bare chip carrier installs an IC bare chip for performing a burn-in test and a functional examination of the bare chip. The carrier consists of an installing unit for installing the bare chip and an interconnecting unit for electrically interconnecting chip electrodes of the bare chip with output electrodes of the interconnecting unit, to be connected to apparatus for the burn-in test and the functional examination. The installing unit is made of aluminium nitride having an expansion rate near of material, ceramic, of the IC bare chip, for making fabrication of installing surface of the IC bare chip easy. The interconnecting unit has an air exchange mechanism by which the IC bare chip can be laid in a space, made by combining the installing unit and the interconnecting unit, constantly filled with inert gas such as nitrogen. The IC bare chip is transported anytime and anywhere as installed in the carrier without being contaminated.

Claims

1. An integrated circuit bare chip carrier for carrying an integrated bare chip installation therein, said integrated bare chip carrier comprising:

means for installing the integrated bare chip, said installing means comprising a depressed surface for installing the integrated bare chip;

interconnecting means combinable with said installing means, for electrically interconnecting chip electrodes on the integrated bare chip with exterior of said integrated bare chip carrier when said installing means installs the integrated bare chip and said installing means and said interconnecting means are combined to one another, said interconnecting means including resilient electrodes for contacting the chip electrodes respectively by using resilient action when said installing means and said interconnecting means are combined to one another and output electrodes for electrically connecting the chip electrodes with the exterior of said integrated circuit bare chip carrier when said installing means and said interconnecting means are combined to one another;

clamping means for clamping, and thereby combining, said installing means and said interconnecting means when said installing means and said interconnecting means are aligned adjacent to one another; and

sealing means for producing a sealed space for the integrated bare chip and said resilient electrodes contacting with the electrodes of a chip respectively and for sealing the integrated bare chip and said resilient electrodes from outside of said integrated circuit bare chip carrier when said installing means and said interconnecting means are combined to one another and clamped by said clamping means.

2. An integrated circuit bare chip carrier according to claim 1, wherein said sealing means comprises an O ring made of elastic inert material arranged so as to enclose the sealed space when said installing means and said interconnecting means are combined to one another and clamped by said clamping means.

3. An integrated circuit bare chip carrier according to claim 1, wherein said interconnecting means further comprises air exchange means for exchanging air in the sealed space with inert gas by exhausting air from the sealed space and filling the sealed space with the inert gas after exhausting and for holding the sealed space in a state filled with the inert gas as far as said installing means and said interconnecting means are combined to one another and clamped by said clamping means.

4. An integrated circuit bare chip carrier according to claim 1, wherein said installing means comprises insulating material having expansion rate being the same order of the integrated bare chip'"'"'s expansion rate.

5. An integrated circuit bare chip carrier according to claim 2, wherein said O ring comprises fluorinated rubber.

6. An integrated circuit bare chip carrier according to claim 4, wherein said insulating material of said installing means comprises aluminum nitride.