Mixed mode output buffer circuit for CMOSIC

• US 5,534,789 A
• Filed: 08/07/1995
• Issued: 07/09/1996
• Est. Priority Date: 08/07/1995
• Status: Expired due to Term

• Current Assignee: Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Ting, Tah-Kang J.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/512,237
• Time in Patent Office: 337 Days
• Field of Search: 326/58, 326/81, 326/83, 326/86, 326/21, 326/27
• US Class Current: 326/21
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Claims

1. An output voltage buffer circuit, comprising:

an internal voltage node;

an output voltage node;

a V_cc voltage supply node;

a ground node;

a modified OR-INVERT gate having inputs and an output wherein said output of said modified OR-INVERT gate is connected to said internal voltage node;

a second OR-INVERT gate having inputs and an output;

an internal voltage clamping circuit connected to said internal voltage node;

an output voltage clamping circuit connected to said internal voltage node and said output voltage node;

a load detection and feedback circuit connected to said output voltage clamping circuit and said output voltage node;

a first output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said first output metal oxide field effect transistor is connected to said internal voltage node, said source of said first output metal oxide field effect transistor is connected to said output voltage node, and said drain of said first output metal oxide semiconductor field effect transistor is connected to said V_cc voltage supply node; and

a second output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said drain of said second output metal oxide field effect transistor is connected to said output voltage node, said gate of said metal oxide field effect transistor is connected to said output of said second OR-INVERT gate, and said source of said second output metal oxide semiconductor field effect transistor is connected to said ground node.

2. The output voltage buffer circuit of claim 1 wherein said internal voltage clamping circuit holds the voltage at said internal voltage node at about 4.3 volts when the voltage at said output voltage node is at the up level.

3. The output voltage buffer circuit of claim 1 wherein said output voltage clamping circuit holds the voltage at said output voltage node at about 3.3 volts when the voltage at said output voltage node is at the up level.

4. The output buffer circuit of claim 1 wherein said load detector and feedback circuit holds the voltage at said output voltage node at about 3.3 volts when the voltage at said output voltage node is at the up level.

5. The output buffer circuit of claim 1 wherein said the voltage at said V_cc voltage supply node is between about 4.0 volts and 6.0 volts.

6. The output buffer circuit of claim 1 wherein said internal voltage clamping circuit further comprises:

a first node;

a second node;

a third node;

a first N channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said first N channel metal oxide semiconductor field effect transistor is connected to said internal voltage node, said gate of said first N channel metal oxide semiconductor field effect transistor is connected to said internal voltage node, and said source of said first N channel metal oxide semiconductor field effect transistor is connected to said first node;

a first P channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said first P channel metal oxide semiconductor field effect transistor is connected to said first node, said gate of said first P channel metal oxide semiconductor field effect transistor is connected to said second node, and said source of said first P channel metal oxide semiconductor field effect transistor is connected to said second node;

a second N channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said second N channel metal oxide semiconductor field effect transistor is connected to said second node, said gate of said second N channel metal oxide semiconductor field effect transistor is connected to said second node, and said source of said second N channel metal oxide semiconductor field effect transistor is connected to said third node; and

a third N channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said third N channel metal oxide semiconductor field effect transistor is connected to said third node, said gate of said third N channel metal oxide semiconductor field effect transistor is connected to said third node, and said source of said third N channel metal oxide semiconductor field effect transistor is connected to said ground node.

7. The output buffer circuit of claim 1 wherein said output voltage clamping circuit further comprises:

a fourth node;

a fifth node;

a second P channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said second P channel metal oxide semiconductor field effect transistor is connected to said output voltage node, said gate of said second P channel metal oxide semiconductor field effect transistor is connected to said internal voltage clamping circuit, and said source of said second P channel metal oxide semiconductor field effect transistor is connected to said fourth node;

a fourth N channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said fourth N channel metal oxide semiconductor field effect transistor is connected to said fourth node, said gate of said fourth N channel metal oxide semiconductor field effect transistor is connected to said fourth node, and said source of said fourth N channel metal oxide semiconductor field effect transistor is connected to said fifth node; and

a fifth N channel metal oxide semiconductor field effect transistor having a drain, a gate, and a source wherein said drain of said fifth N channel metal oxide semiconductor field effect transistor is connected to said fifth node, said gate of said fifth N channel metal oxide semiconductor field effect transistor is connected to said internal voltage node, and said source of said fifth N channel metal oxide semiconductor field effect transistor is connected to said ground node.

8. The output buffer circuit of claim 1 wherein said load detection and feedback circuit further comprises:

an NPN bipolar transistor having a collector, a base, and an emitter wherein said collector of said NPN bipolar transistor is connected to said V_cc voltage supply node, said emitter of said NPN bipolar transistor is connected to said output voltage node, and said base of said NPN bipolar transistor is connected to said output of said modified OR-INVERT gate; and

a connection between one of said inputs of said modified OR-INVERT gate and said output voltage clamping circuit.

9. The output buffer circuit of claim 8 wherein said NPN bipolar transistor is a parasitic transistor in an integrated circuit element containing metal oxide semiconductor field effect transistors.

10. The output buffer circuit of claim 1 wherein said internal voltage clamping circuit, said output voltage clamping circuit, and said load detection and feedback circuit are contained in a single integrated circuit element.