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Mixed mode output buffer circuit for CMOSIC

  • US 5,534,789 A
  • Filed: 08/07/1995
  • Issued: 07/09/1996
  • Est. Priority Date: 08/07/1995
  • Status: Expired due to Term
First Claim
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1. An output voltage buffer circuit, comprising:

  • an internal voltage node;

    an output voltage node;

    a Vcc voltage supply node;

    a ground node;

    a modified OR-INVERT gate having inputs and an output wherein said output of said modified OR-INVERT gate is connected to said internal voltage node;

    a second OR-INVERT gate having inputs and an output;

    an internal voltage clamping circuit connected to said internal voltage node;

    an output voltage clamping circuit connected to said internal voltage node and said output voltage node;

    a load detection and feedback circuit connected to said output voltage clamping circuit and said output voltage node;

    a first output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said first output metal oxide field effect transistor is connected to said internal voltage node, said source of said first output metal oxide field effect transistor is connected to said output voltage node, and said drain of said first output metal oxide semiconductor field effect transistor is connected to said Vcc voltage supply node; and

    a second output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said drain of said second output metal oxide field effect transistor is connected to said output voltage node, said gate of said metal oxide field effect transistor is connected to said output of said second OR-INVERT gate, and said source of said second output metal oxide semiconductor field effect transistor is connected to said ground node.

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