Mixed mode output buffer circuit for CMOSIC
First Claim
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1. An output voltage buffer circuit, comprising:
- an internal voltage node;
an output voltage node;
a Vcc voltage supply node;
a ground node;
a modified OR-INVERT gate having inputs and an output wherein said output of said modified OR-INVERT gate is connected to said internal voltage node;
a second OR-INVERT gate having inputs and an output;
an internal voltage clamping circuit connected to said internal voltage node;
an output voltage clamping circuit connected to said internal voltage node and said output voltage node;
a load detection and feedback circuit connected to said output voltage clamping circuit and said output voltage node;
a first output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said first output metal oxide field effect transistor is connected to said internal voltage node, said source of said first output metal oxide field effect transistor is connected to said output voltage node, and said drain of said first output metal oxide semiconductor field effect transistor is connected to said Vcc voltage supply node; and
a second output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said drain of said second output metal oxide field effect transistor is connected to said output voltage node, said gate of said metal oxide field effect transistor is connected to said output of said second OR-INVERT gate, and said source of said second output metal oxide semiconductor field effect transistor is connected to said ground node.
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Abstract
This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.
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Citations
10 Claims
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1. An output voltage buffer circuit, comprising:
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an internal voltage node; an output voltage node; a Vcc voltage supply node; a ground node; a modified OR-INVERT gate having inputs and an output wherein said output of said modified OR-INVERT gate is connected to said internal voltage node; a second OR-INVERT gate having inputs and an output; an internal voltage clamping circuit connected to said internal voltage node; an output voltage clamping circuit connected to said internal voltage node and said output voltage node; a load detection and feedback circuit connected to said output voltage clamping circuit and said output voltage node; a first output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said first output metal oxide field effect transistor is connected to said internal voltage node, said source of said first output metal oxide field effect transistor is connected to said output voltage node, and said drain of said first output metal oxide semiconductor field effect transistor is connected to said Vcc voltage supply node; and a second output metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said drain of said second output metal oxide field effect transistor is connected to said output voltage node, said gate of said metal oxide field effect transistor is connected to said output of said second OR-INVERT gate, and said source of said second output metal oxide semiconductor field effect transistor is connected to said ground node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification