Self-clocking pipeline register

• US 5,534,796 A
• Filed: 04/21/1995
• Issued: 07/09/1996
• Est. Priority Date: 04/21/1995
• Status: Expired due to Term

• Current Assignee: ZiiLabs Inc., Ltd. (Creative Technology Ltd.)
• Original Assignee: Intergraph Corporation (Hexagon AB)
• Inventors: Edwards, Stephen W.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/427,076
• Time in Patent Office: 445 Days
• Field of Search: 326/93, 326/95, 326/98, 327/141
• US Class Current: 326/93
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A control module for controlling a data register, a self-clocking data register controlled by such a module and a pipeline of self-clocked pipeline registers. The localized control module includes a flip-flop for indicating whether the data register being controlled is occupied or vacant. Each module includes state machine logic for generating an enable output to the pipeline register when the flip-flop indicates the register was vacant and a load signal indicating data is available for loading into the register has been received. The localized control may be further modified to provide look-ahead in which an enable output is also generated when a load signal has been received and an unload signal has been received.

Claims

1. A module for controlling a pipeline register comprising:

a flip-flop for indicating whether the pipeline register is occupied or vacant;

load means for receiving a load signal when data is available for loading into the pipeline register; and

state machine logic responsive to said flip-flop and said load means so as to generate an enable output to the pipeline register when said flip-flop indicates vacant and said load means has received a load signal.

2. The module of claim 1 further comprising a clock to provide a periodic clock signal.

3. The module of claim 2 wherein said flip-flop is connected so as to switch from vacant to occupied on clock signal when said flip-flop was initially vacant and said load means has received a load signal.

4. The module of claim 2 further comprising unload means for receiving an unload signal indicating that the pipeline register is being unloaded.

5. The module of claim 4 wherein said flip-flop is connected so as to switch from occupied to vacant upon a clock signal when said unload means has received an unload signal.

6. The module of claim 4 wherein said state machine logic also generates an enable output to the pipeline register when said load means has received a load signal and said unload means has received an unload signal.

7. The module of claim 4 wherein said flip-flop is connected so as to indicate occupied upon a clock signal when said load means has received a load signal.

8. A self-clocking pipeline register comprising:

a data register connected to receive data in response to an enable signal;

a flip-flop for indicating whether said data register is occupied or vacant;

load means for receiving a load signal when data is available for loading into said data register; and

state machine logic connected to said flip-flop and said load means and having an output connected to said data register so as to generate the enable signal on the output when said flip-flop indicates vacant and said load means has received a load signal.

9. The pipeline register of claim 8 further comprising a clock to provide a periodic clock signal.

10. The pipeline register of claim 9 wherein said flip-flop is connected so as to switch from vacant to occupied upon a clock signal when said flip-flop was initially vacant and said load means has received a load signal.

11. The pipeline register of claim 9 wherein said data register comprises a multi-bit data register.

12. The pipeline register of claim 9 further comprising unload means for receiving an unload signal indicating that said data register is being unloaded.

13. The pipeline register of claim 12 wherein said flip-flop is connected so as to switch from occupied to vacant upon a clock signal when said unload means has received an unload signal.

14. The pipeline register of claim 12 wherein said state machine logic also generates an enable signal when said load means has received a load signal and said unload means has received an unload signal.

15. The pipeline register of claim 12 wherein said flip-flop is connected so as to indicate occupied upon a clock signal when said load means has received a load signal.

16. A data pipeline comprising:

a plurality of stages of data registers each stage connected to receive data in response to an enable signal;

a plurality of flip-flops each connected to one of said stages of data registers for indicating whether the respective stage is occupied or vacant;

a plurality of load means each coupled to one of said flip-flops for receiving a load signal when data is available for loading into the respective stage; and

a plurality of state machines each connected to one of said flip-flops and the respective load means and having an output connected to the respective stage so as to generate the enable signal on the output when said one of said flip-flops indicates vacant and the respective load means has received a load signal.

17. The data pipeline of claim 16 further comprising a clock to provide a periodic clock signal.

18. The data pipeline of claim 17 wherein each of said flip-flops is connected so as to switch from vacant to occupied upon a clock signal when said flip-flop was initially vacant and the respective load means has received a load signal.

19. The data pipeline of claim 17 further comprising a plurality of unload means each coupled to one of said flip-flops for receiving an unload signal indicating that the respective stage is being unloaded.

20. The data pipeline of claim 17 wherein at least one of said flip-flops is connected so as to switch from occupied to vacant upon a clock signal when the respective unload means has received an unload signal.

21. The data pipeline of claim 17 wherein at least one of said state machines also generates an enable signal when the respective load means has received a load signal and the respective unload means has received an unload signal.

22. The data pipeline of claim 17 wherein at least one of said flip-flops is connected so as to indicate occupied upon a clock signal when the respective load means has received a load signal.