Parallel phase-locked loop oscillator circuits with average frequency calculation of input stage loop

• US 5,534,822 A
• Filed: 01/31/1994
• Issued: 07/09/1996
• Est. Priority Date: 09/20/1993
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamamoto, Chiyoko, Taniguchi, Atsuki
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US08/189,462
• Time in Patent Office: 890 Days
• Field of Search: 331/1 A, 331/2, 331/18, 331/11, 331/17, 375/376, 327/141, 327/147, 327/151
• US Class Current: 331/2
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/146 by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence

Abstract

A phase-locked oscillator circuit with a broad pull-in frequency range generates a stable output signal synchronized to the phase of an input signal. An input-stage phase-locking circuit wherein the phase of a first frequency-converted output signal from a 1st frequency-conversion section is compared by a 1st phase-comparison circuit with the phase of the input signal and the phase of the 1st frequency-converted output signal is controlled. A processing section determines the frequency component of the input signal based on the phase-comparison output signal from the 1st phase-comparison circuit. An output-stage phase-locking circuit compares the phase of a 2nd frequency-conversion section with the phase of the input signal in a 2nd phase-comparison circuit. The phase of the 2nd frequency-conversion section is controlled based on the resulting phase-comparison output signal and the phase comparison output signal from the 1st phase-comparison circuit. Thus, the phase of the 2nd frequency-converted output signal is controlled.

Claims

1. A phase-locked oscillator circuit comprising:

an input-stage phase-locking circuit (2) which compares a phase of a 1st frequency-converted output signal derived by frequency division with a phase of an input signal by means of a 1st phase-comparison circuit (1), and which has a feedback loop which controls the phase of said 1st frequency-converted output signal;

a processing section (3) including an average-frequency calculation circuit which determines an average frequency of said input signal, based on a phase-comparison output signal of said 1st phase comparison circuit (1) of said input-stage phase-locking circuit (2); and

an output-stage phase-locking circuit (5) which compares a phase of a 2nd frequency-converted output signal derived by frequency division with the phase of said input signal by means of a 2nd phase-comparison circuit (4), and which has a feedback loop which controls the phase of said 2nd frequency-converted output signal based on a phase-comparison output of said 2nd phase-comparison circuit (4) and a processed output signal from said processing section (3).

2. A phase-locked oscillator circuit according to claim 1, wherein a time constant of said input-stage phase-locking circuit (2) is made short and time constant of said output-stage phase-locking circuit (5) is made long.

3. A phase-locked oscillator circuit according to claim 1, wherein said input-stage phase-locking circuit (2) includes said 1st phase-comparison circuit (1), a 1st programmable-ratio frequency-division circuit which generates said 1st frequency-converted output signal, and a 1st lead/lag control section which performs switching control of a frequency division ratio of said 1st programmable-ratio frequency-division circuit, based on a phase-comparison output signal of said 1st phase-comparison circuit (1).

4. A phase-locked oscillator circuit according to claim 1, wherein said output-stage phase-locking circuit (5) includes said 2nd phase-comparison circuit (4), said 2nd programmable-ratio frequency-division circuit which generates said 2nd frequency-converted output signal, and a 2nd lead/lag control section which performs switching control of a division ratio of said 2nd programmable-ratio frequency division circuit based on a phase-comparison output signal of said 2nd phase-comparison circuit 141 and on a processed output signal of said processing section (3).

5. A phase-locked oscillator circuit according to claim 3, wherein said 1st phase-comparison circuit (1) of said input-stage phase-locking circuit (2) is configured to detect whether the phase of said 1st frequency-converted output signal leads or lags with respect to said input signal.

6. A phase-locked oscillator circuit according to claim 1, wherein said processing section (3) includes a counter which counts either a lead or lag phase-comparison output signal from said 1st phase-comparison circuit (1) of said input-stage phase-locking circuit (2), and an average-value calculating section which determines a time average of the count of said counter.

7. A phase-locked oscillator circuit according to claim 4, wherein said 2nd phase-comparison circuit (4) of said output-stage phase-locking circuit (5) detects whether the phase of said 2nd frequency-converted output signal leads or lags with respect to said input signal.

8. A phase-locked oscillator circuit according to claim 1, wherein said 1st frequency-converted output signal of said input-stage phase-locking circuit (2) and said 2nd frequency-converted output signal of said output-stage phase-locking circuit (5) are produced by 1st and 2nd programmable-ratio frequency-division circuits, respectively, which divide a frequency of an output signal from a fixed-frequency oscillator.

9. A phase-locked oscillator circuit according to claim 1, wherein said processed output signal which is applied to said output-stage phase-locking circuit (5) from said processing section (3), is fixed by a holdover signal.