Video signal interface

• US 5,534,883 A
• Filed: 04/16/1993
• Issued: 07/09/1996
• Est. Priority Date: 04/24/1992
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Koh, Yoshihiro
• Primary Examiner(s): Chan, Wing F.
• Assistant Examiner(s): CHIN, VIVIAN C
• Application Number:
  US08/047,207
• Time in Patent Office: 1,180 Days
• Field of Search: 345/1, 345/3, 345/98, 345/132, 345/154, 345/155, 345/147, 345/89, 345/185
• US Class Current: 345/3.2
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A video signal interface device that converts display data in serial format for a first display device, e.g. CRT display, to display data appropriate to a second display device, e.g. LCD panel. The second display device can execute binary display and carry out gray-scale display as a pseudo operation by switching with every frame. The interface comprises S/P converter means that converts the display data of serial format to parallel data, pattern generating means that holds gray-scale pattern data according to the number of gradations and outputs with every frame unit of the second display device data corresponding to the type of binary display in accordance with the gray-scale pattern data, memory means that stores display for the second display device, data generating means that generates display data of parallel format based on both the output of the pattern generating means and the displayed gradations of the converted display data, memory control means that writes data generated by the data generating means to the memory means and that reads the data from the memory means, address generating means that generates addresses for the memory means, and output means that outputs data read from the memory means at timing matched with the operation of the second display device.

Claims

1. In a video signal interface that converts display data in serial format for a first display device to display data appropriate to a second display device, said second display device having pixels capable of binary display and carrying out gray-scale display as a pseudo operation by switching with every frame between the binary displays to be carried out at every pixel,

a video signal interface comprising:

S/P converter means for converting said serially formatted display data to parallel data;

pattern generating means for holding gray-scale pattern data according to the number of gradations that can be displayed by said second display device and outputting with every frame unit of said second display device data corresponding to the type of binary display in accordance with said gray-scale pattern data;

memory means, having a number of bits equal to half the number of pixels of said second display means, for storing said display data appropriate to said second display means;

data generating means for generating display data of parallel format for use in said second display device based on both the output of said pattern generating means and the gradations of said converted display data;

memory control means for writing data generated by said data generating means to said memory means and for reading the data from said memory means;

address generating means for generating addresses corresponding to said memory means; and

output means for outputting data read from said memory means at timing matched with the operation of said second display device;

wherein the correlation between the memory addresses and the pixels of the second display is fixed;

wherein said pattern generating means has both a register and a gray-scale pattern generating circuit, said register being accessible to outside of said video signal interface and holding gray-scale pattern data, and said gray-scale pattern generating circuit outputting data corresponding to one of either binary display based on said gray-scale pattern data and in accordance with a clock signal to said LCD device.

2. A video signal interface according to claim 1 wherein said first display device carries out display at only one pixel with every cycle of the clock signal and in addition performs display of one screen by successively carrying out display to each pixel, and said second display device carries out display at a plurality of pixels with every cycle of the clock signal based on display data in parallel format.

3. A video signal interface according to claim 2 wherein one screen of said second display device is logically divided into two equal portions, a first portion and a second portion, in which display on said first portion and said second portion is carried out at the same timing.

4. A video signal interface according to claim 2, wherein said first display device is a CRT (cathode-ray tube) display device and said second display device is an LCD (Liquid Crystal Display) device.

5. A video signal Interface according to claim 4 wherein the screen of said LCD device is logically divided into two equal portions, a first portion and a second portion, in which display to said first portion and said second portion is carried out at the same timing.

6. A video signal interface according to claim 5 wherein the frame frequency of said LCD device coincides with the frame frequency of said CRT display device, and wherein display data is outputted such that the display of one screen on said LCD display device corresponds to the display of one screen on said CRT display device.

7. A video signal interface according to claim 6, wherein

each bit in said memory means has a one-to-one correspondence with each pixel of said LCD device,

during the time when display data for said CRT display device is data corresponding to said first portion, data corresponding to said first portion is written sequentially to said memory means while at the same time data corresponding to said first and said second portions is alternately read from said memory means, and

during the time when display data for said CRT display device is data corresponding to said second portion, data corresponding to said second portion is written sequentially to said memory means while at the same time data corresponding to said first and second portions is alternately read from said memory means.

8. A video signal interface according to claim 4, wherein said CRT display device is capable of displaying color, the display data for every pixel being of three bits, the three bits of said display data corresponding respectively to the colors red, green and blue.

9. A video signal interface according to claim 8 wherein the display of eight gradations may be performed on said LCD device.

10. A video signal interface according to claim 5, wherein the frame frequency of said LCD device is twice the frame frequency of said CRT display device, and wherein display data is outputted such that the display of two screens on said LCD display device corresponds to the display of one screen on said CRT display device.

11. A video signal interface according to claim 10, wherein

each bit in said memory means has a duplicated correspondence with one pixel in said first portion and one pixel in said second portion,

during the time when display data for said CRT display device is data corresponding to said first portion, data corresponding to said first portion is written sequentially to said memory means, and at the same time, data corresponding to said second portion is sequentially read from said memory means, data corresponding to said first portion is directly outputted to said LCD device, and

during the time when display data for said CRT display device is data corresponding to said second portion, data corresponding to said second portion is written sequentially to said memory means, while at the same time, data corresponding to said first portion is sequentially read from said memory means, and data corresponding to said second portion is directly outputted to said LCD device.

12. A video signal interface according to claim 1, wherein said gray-scale pattern data applied to adjoining pixels in the same line are different from one another.

13. A video signal interface according to claim 1, wherein said gray-scale pattern data applied to a pixel in one frame and in a successive frame are different from one another.