Apparatus for reducing flickers of encoder when digitally converting video signals from non-interlaced to interlaced format

• US 5,534,936 A
• Filed: 02/17/1995
• Issued: 07/09/1996
• Est. Priority Date: 02/17/1994
• Status: Expired due to Fees

• Current Assignee: Goldstar Jewellery LLC
• Original Assignee: Goldstar Jewellery LLC
• Inventors: Kim, Hae Jong
• Primary Examiner(s): Kostak, Victor R.
• Assistant Examiner(s): Acosta, Juan G.
• Application Number:
  US08/390,576
• Time in Patent Office: 508 Days
• Field of Search: 348/910, 348/448, 348/458, 348/447
• US Class Current: 348/448
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction
• CPC Class Codes: Y10S 348/91 Flicker reduction

Abstract

An improved apparatus for reducing flickers of an encoder capable of advantageously reducing flickers occurred when video signals are converted from a non-interlace scanning method to an interlace scanning method in the digital method, which includes a graphic controller for outputting a pixel signal by a line unit and for outputting a pixel clock, a horizontal synchronous signal and a vertical synchronous signal; a synchronous signal converter for converting a pixel clock, a horizontal synchronous signal and a vertical synchronous signal outputted from the graphic controller to a pixel clock, a horizontal synchronous signal and a vertical synchronous signal of an interlace scanning method; a control signal generator for outputting a control signal by receiving a pixel clock, a horizontal synchronous signal and a vertical synchronous signal of an interlace scanning method outputted from the synchronous signal converter; a line store unit for selecting a pixel data corresponding to nth even scanning line among the output signals of the graphic controller and for writing/reading the selected pixel data in accordance with a control signal of the control signal generator; a multiplexer for selecting and outputting a pixel data of a scanning line adjacent thereto among the output signals of the line store unit; a digital added for adding a pixel data of a scanning line adjacent thereto outputted from the multiplexer; a shifting unit for computing average value of pixel data at a scanning line adjacent thereto by receiving an output signal of the digital adder; an encoder for encoding a signal outputted from the shifting unit; and an oscillator for transmitting clocks to the control signal generator and the shifting unit.

Claims

1. An apparatus for reducing flickers of an encoder, comprising:

graphic control means for outputting pixel data corresponding to an analog output from a line scanning unit, and for outputting a pixel clock signal, a horizontal synchronous signal and a vertical synchronous signal;

synchronous signal covering means for converting a pixel clock signal, a non-interlaced horizontal synchronous signal and non-interlaced vertical synchronous signal outputted from the graphic control means to a pixel clock, a horizontal synchronous signal and a vertical synchronous signal of an interlace scanning method;

control signal generating means for outputting a control signal by receiving a pixel clock, a horizontal synchronous signal and a vertical synchronous signal of a interlace scanning method outputted from the synchronous signal converting means;

line store means for selecting pixel data corresponding to nth even scanning line of the pixel data from the graphic control means and for writing/reading the selected pixel data in accordance with a control signal of the control signal generating means;

multiplexing means for selecting and outputting a pixel data pair corresponding to adjacent scanning lines stored in the line store means;

digital addition means for adding pixels from a pixel data pair from the multiplexer;

shift means for computing average value of pixel data at a scanning line adjacent thereto by receiving an output signal of the digital addition means;

encoding means for encoding a signal outputted from the shift means; and

oscillating means for transmitting clocking signals to the control signal generator and the shifting unit.

2. The apparatus of claim 1, wherein said line store means includes a plurality of FIFO memories for writing pixel data of the selected scanning line onto at least two memories when writing in accordance with a control signal of the control signal generating means and for reading pixel data from the FIFO memory in which the pixel data of the adjacent scanning line are written when reading in accordance with a control signal of the control signal generating means.

3. The apparatus of claim 1, wherein said multiplexing means includes a plurality of latch pairs for latching pixel data of the adjacent scanning line and further includes a plurality of buffers for buffering/outputting data from the latch pairs in accordance with a control signal outputted from the control signal generating means.

4. The apparatus of claim 1, wherein said control signal generating means includes

a counter for counting the horizontal synchronous signal and the vertical synchronous signal from the synchronous converting means;

and

a logic unit, responsive to the counter, the horizontal and vertical synchronous signals from the synchronous signal converting means and the clocking signals from the oscillator, for outputting a control signal for controlling the line store means and the multiplexing means.

5. The apparatus of claim 4, wherein said counter is enabled for counting when the vertical synchronous signal is in a high state, said counter counting instances of when the horizontal synchronous signal goes to a binary high state and said counter is inactive when the vertical synchronous signal is in a binary low state.

6. An apparatus for digitally reducing flicker associated with an encoder that converts non-interlaced video signals to interlaced video signals, the apparatus receiving interlaced pixel data output from a line scanner and non-interlaced timing signals associated therewith, the apparatus comprising:

input means for receiving the interlaced pixel data;

timing means for converting non-interlaced timing signals to interlaced timing signals;

a memory, operatively connected to the input means and the timing means, for storing pixel data;

a multiplexer, operatively connected to the memory and the timing means, for reading pixels from selected adjacent interlaced scanning lines stored in the memory;

averaging means, operatively connected to the multiplexer and the timing means, for averaging pixels from adjacent scanning lines; and

an encoder, operatively connected to the averaging means for encoding the averaged pixels.

7. An apparatus as in claim 6, wherein the memory comprises:

at least three FIFO buffers.

8. An apparatus as in claim 6, wherein the multiplexer comprises:

at least one pair of latches for each interlaced scanning line stored in the memory.