Circuit arrangement for an inductive position indicator

• US 5,535,142 A
• Filed: 07/21/1993
• Issued: 07/09/1996
• Est. Priority Date: 07/22/1992
• Status: Expired due to Fees

• Current Assignee: Thomas Theil, Walter Mehnert
• Original Assignee: Thomas Theil, Walter Mehnert
• Inventors: Mehnert, Walter, Theil, Thomas
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Stamber, Eric W.
• Application Number:
  US08/094,574
• Time in Patent Office: 1,084 Days
• Field of Search: 33/706, 33/708, 33/784, 364/559, 324/207.17, 324/207.25, 324/207.16, 324/207.15
• US Class Current: 702/189
• CPC Class Codes: G01B 7/003 for measuring position, not involving coordinate determination coordinate measuring G01B7/004
• CPC Class Codes: G01D 5/2046 by a movable ferromagnetic element, e.g. a core
• CPC Class Codes: G01D 5/2258 by a movable ferromagnetic element, e.g. core

Abstract

A circuit arrangement for an inductive position indicator which comprises a measurement coil arrangement having a plurality of measurement coils forming at least first and second groups, each of which supplies a measurement coil signal that varies with the position to be monitored, includes a computing circuit which, to produce a measurement signal, interlinks at least two signals derived from the measurement coil signals, in accordance with a predetermined algorithm. The circuit arrangement further includes a multiplexer for feeding a variable selection of measurement coil signals to the further processing, to achieve a high level of resolution and measurement accuracy.

Claims

1. A circuit arrangement for an inductive position indicator which monitors a position to be monitored which a first one of two bodies being movable with respect to each other occupies with respect to a second one of said two bodies, said position indicator comprising

at least one exciter coil to which an ac voltage is fed to generate a magnetic flux,

a measurement coil arrangement having a plurality of measurement coils from which at least two different measurement coil signals can be taken simultaneously,

flux guide means of ferromagnetic material which guide the magnetic flux generated by said exciter coil such that the magnetic flux through at least one of said measurement coils and thereby at least one of said at least two different measurement coil signals varies in dependence on said position to be monitored, said circuit arrangement comprising

a multiplexer for taking both of said at least two different measurement coil signals and feeding them one by one to an input amplifier providing amplified measurement coil signals, said input amplifier being part of

a single-channel signal processing means providing a first single-channel output signal when a first one of said at least two different measurement coil signals is fed to said input amplifier and providing a second single-channel output signal when a second one of said at least two different measurement coil signals is fed to said input amplifier,

a de-multiplexer for taking said first and second single-channel output signals one by one and feeding said first one of them into a first signal channel and said second one of them into a second signal channel each of said first and second signal channels leading to one of two inputs of

a computing circuit means which requires said first and second single-channel output signals at the same time in order to produce a computing circuit output signal from which a measurement signal can be derived which represents said position to be monitored,

wherein at least said first signal channel comprises a circuit means for storing or delaying said first single-channel output signal fed thereto by said de-multiplexer until said second single-channel output signal is fed by said de-multiplexer to said second signal channel.

2. A circuit arrangement as set forth in claim 1, wherein said single-channel signal processing means comprises a circuit means for weighting with factors said amplified measurement coil signals from said input amplifier and wherein said computing circuit means is adapted to generate a computing circuit output signal which contains the sum of said first and second single-channel output signals fed to its at least two inputs at the same time.

3. A circuit arrangement as set forth in claim 1, wherein said computing circuit means comprises a circuit means for summing and weighting with factors said first and second single-channel output signals so that said computing circuit output signal contains the weighted sum of said first and second single-channel output signals fed to its at least two inputs at the same time.

4. A circuit arrangement as set forth in claim 2 or 3, wherein circuit means for generating and varying a control signal for said factors are provided said control signal being varied until said computing circuit output signal obtains a value which is equal to a predetermined value.

5. A circuit arrangement as set forth in claim 2, wherein said circuit means for weighting with factors is a multiplying digital-analog converter having an analog voltage input to which said amplified measurement coil signals which are to be weighted are applied, and a digital input, and wherein a first counter is provided which counts output pulses from a voltage controlled oscillator means whose control input receives said computing circuit output signal, said first counter being operable to count up when the value of said computing circuit output signal is lower than said predetermined value and to count down when the value of said computing circuit output signal is higher than said predetermined value.

6. A circuit arrangement as set forth in claim 3, wherein said circuit means for summing and weighting with factors comprises a resistor series circuit which comprises several resistors and has two end points and tappings between said resistors, each of said end points and each of said tappings being connected to a corresponding input of a second multiplexer by an individual line and said end points being the two inputs of said computing circuit means to which said first and second single-channel output signals are applied, and a multiplying digital-analog converter having two analog voltage inputs to which said second multiplexer connects selection of two of said individual lines from said end points and tappings, and a digital input, and wherein a first counter is provided which counts output pulses from a voltage controlled oscillator means whose control input receives said computing circuit output signals, said first counter being operable to count up when the value of said computing circuit output signal is lower than said predetermined value and to count down when the value of said computing circuit output signal is higher than said predetermined value.

7. A circuit arrangement as set forth in claim 5 or 6, further including a second counter which, for each period of time needed for obtaining a computing circuit output signal counts the output pulses of said voltage-controlled oscillator means such that it starts from a count value of zero and ends with an auxiliary count result which is added to a simultaneously obtained count result of said first counter when said value of said computing circuit output signal is lower than said predetermined value and is subtracted from a simultaneously obtained count result of said first counter when said value of said computing circuit output signal is higher than said predetermined value.

8. A circuit arrangement as set forth in claim 1, wherein each of said first and second signal channels leading from said de-multiplexer to said computing circuit means comprises a circuit means for storing or delaying the respective first or second single-channel output signal from said de-multiplexer.

9. A circuit arrangement as set forth in claim 8, wherein each of said circuit means for storing or delaying said first or second single-channel output signals comprises a capacitor, and wherein said de-multiplexer comprises a controllable switch means adapted to feed said first single-channel output signal to said capacitor in said first signal channel and to feed said second single-channel output signal to said capacitor in said second signal channel.

10. A circuit arrangement as set forth in claim 9, wherein said first and second single-channel output signals are ac voltage signals and wherein said controllable switch means is adapted to be closed for a time period at a moment in which the respective one of said first and second single-channel output signals is in a range where it has a low voltage gradient dU/dt, said controllable switch means also being adapted to be opened again in said range.

11. A circuit arrangement as set forth in claim 10, wherein said ac voltage signals are sinusoidal voltages having positive and negative peaks and wherein closing and opening of said controllable switch means is effected near one of said peaks.

12. A circuit arrangement as set forth in claim 10 and further including a system control means for controlling opening and closing of said controllable switch means, said system control means determining switching times by evaluating said ac voltage which is fed to said exciter coil of said inductive position indicator.

13. A circuit arrangement as set forth in claim 10, wherein whenever one of said controllable switch means is opened individual portions of the circuit arrangement which can possibly form sources of interference voltage peaks are stopped for a short period of time which begins prior to and terminates after said time period during which the respective controllable switch means is closed.

14. A circuit arrangement as set forth in claim 1 with an input amplifier having an input offset voltage which cannot be neglected, wherein said multiplexer is adapted to short-circuit the input of said input amplifier for selectable periods of time thereby to compensate for the input offset voltage of set input amplifier and wherein each signal produced by said input amplifier in said period of time is used as a correction value for the computing circuit output signal obtained a short time before or after the respective period of time.

15. A circuit arrangement as set forth in claim 14, wherein said circuit arrangement further includes a signal storage circuit means for intermediate storage of a signal reproducing the input offset voltage of said input amplifier.

16. A circuit arrangement as set forth in claim 1, wherein said measurement coil signals are difference signals.

17. A circuit arrangement as set forth in claim 1, wherein said multiplexer comprises controllable switch means which can be controlled to connect two or more of said measurement coils with each other in order to obtain one common measurement coil signal from these connected measurement coils.