Semiconductor memory device for inputting and outputting data in a unit of bits
First Claim
1. A multibit memory device comprising:
- a memory cell array composed of mixed memory cells corresponding to different IO bits;
a plurality of data input/output terminals corresponding respectively to IO bits, for inputting and outputting data in a parallel fashion to and from said memory cell array, said data input/output terminals being classified into a first data input/output terminal and a second data input/output terminal;
an address terminal for inputting an address;
internal data buses associated respectively with the IO bits and connected to said memory cell array;
test mode entry signal generating means for generating a test mode entry signal indicative of entry into a test mode;
pseudo-address generating means connected to said address terminal, for generating a pseudo-address in said test mode; and
connecting means responsive to said test mode entry signal for selecting one of said internal data buses depending on said pseudo-address and connecting the selected one of the internal data buses to said first data input/output terminal in said test mode.
2 Assignments
0 Petitions
Accused Products
Abstract
A multibit semiconductor memory device for inputting and outputting data in a parallel fashion in a unit of bits. The multibit memory has a memory cell array composed of mixed memory cells corresponding to different IO bits, data I/O terminals corresponding respectively to IO bits, an address terminal for inputting an address and internal data buses associated respectively with the IO bits and connected to the memory cell array. Further, the memory device has a test mode entry signal generator for generating a test mode entry signal indicative of entry into a test mode, a pseudo-address generator connected to the address terminal, for generating a pseudo-address in the test mode, and a connecting circuit responsive to the test mode entry signal for selecting one of the internal data buses depending on the pseudo-address and connecting the selected bus to predetermined one of the data I/O terminals.
-
Citations
7 Claims
-
1. A multibit memory device comprising:
-
a memory cell array composed of mixed memory cells corresponding to different IO bits; a plurality of data input/output terminals corresponding respectively to IO bits, for inputting and outputting data in a parallel fashion to and from said memory cell array, said data input/output terminals being classified into a first data input/output terminal and a second data input/output terminal; an address terminal for inputting an address; internal data buses associated respectively with the IO bits and connected to said memory cell array; test mode entry signal generating means for generating a test mode entry signal indicative of entry into a test mode; pseudo-address generating means connected to said address terminal, for generating a pseudo-address in said test mode; and connecting means responsive to said test mode entry signal for selecting one of said internal data buses depending on said pseudo-address and connecting the selected one of the internal data buses to said first data input/output terminal in said test mode. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
Specification