Semiconductor memory device for inputting and outputting data in a unit of bits

• US 5,535,163 A
• Filed: 11/01/1994
• Issued: 07/09/1996
• Est. Priority Date: 11/01/1993
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Matsui, Yoshinori
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/332,727
• Time in Patent Office: 616 Days
• Field of Search: 365/200, 365/201, 365/189.01, 365/189.03, 371/10.1, 371/10.2, 371/21.1, 371/21.3, 371/27
• US Class Current: 365/201
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A multibit semiconductor memory device for inputting and outputting data in a parallel fashion in a unit of bits. The multibit memory has a memory cell array composed of mixed memory cells corresponding to different IO bits, data I/O terminals corresponding respectively to IO bits, an address terminal for inputting an address and internal data buses associated respectively with the IO bits and connected to the memory cell array. Further, the memory device has a test mode entry signal generator for generating a test mode entry signal indicative of entry into a test mode, a pseudo-address generator connected to the address terminal, for generating a pseudo-address in the test mode, and a connecting circuit responsive to the test mode entry signal for selecting one of the internal data buses depending on the pseudo-address and connecting the selected bus to predetermined one of the data I/O terminals.

Claims

1. A multibit memory device comprising:

a memory cell array composed of mixed memory cells corresponding to different IO bits;

a plurality of data input/output terminals corresponding respectively to IO bits, for inputting and outputting data in a parallel fashion to and from said memory cell array, said data input/output terminals being classified into a first data input/output terminal and a second data input/output terminal;

an address terminal for inputting an address;

internal data buses associated respectively with the IO bits and connected to said memory cell array;

test mode entry signal generating means for generating a test mode entry signal indicative of entry into a test mode;

pseudo-address generating means connected to said address terminal, for generating a pseudo-address in said test mode; and

connecting means responsive to said test mode entry signal for selecting one of said internal data buses depending on said pseudo-address and connecting the selected one of the internal data buses to said first data input/output terminal in said test mode.

2. The multibit memory device according to claim 1, wherein said connecting means comprises buffers connected respectively to said internal data buses and selectively operable in response to said pseudo-address, and a transfer gate circuit associated with said second data input/output terminal for disconnecting said second data input/output terminal and connecting a corresponding one of said buffers to said first data input/output terminal in response to said test mode entry signal.

3. The multibit memory device according to claim 1, wherein:

said connecting means connects said data input/output terminals respectively to said internal data buses in a normal operation mode which is distinct from said test mode.

4. The multibit memory device according to claim 2, wherein:

said connecting means connects said buffers respectively to said data input/output terminals in a normal operation mode which is distinct from said test mode.

5. The multibit memory device according to claim 1, wherein said test mode entry signal generating means comprises a terminal which is unused in a normal operation mode, and a circuit for generating said test mode entry signal when a voltage higher than a predetermined threshold voltage is applied to said terminal.

6. The multibit memory device according to claim 1, comprising a plurality of address terminals, said pseudo-address generating means being connected to a predetermined one of said address terminals.

7. The multibit memory device according to claim 6, wherein column and row addresses are supplied in a time sharing manner to the multibit memory device, said pseudo-address generating means is connected to one or more than one of said address terminals which are used by row addresses but not by column addresses, and decodes a signal supplied to said one or more than one of the address terminals to generate the pseudo-address.