Multiport analyzing with time stamp synchronizing

• US 5,535,193 A
• Filed: 02/09/1995
• Issued: 07/09/1996
• Est. Priority Date: 02/09/1995
• Status: Expired due to Term

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: Wandel & Goltermann Technologies, Inc. (Lumentum Holdings Inc.)
• Inventors: Zhang, Jing, Gramley, Kenneth R.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/385,900
• Time in Patent Office: 516 Days
• Field of Search: 370/13, 370/14, 370/17, 370/60, 370/60.1, 370/85.1, 370/85.2, 370/94.1, 370/94.2, 370/100.1, 370/105, 370/105.1, 370/105.2, 371/20.1, 371/20.2, 340/825.06, 375/224, 375/228, 379/9, 379/10, 379/12, 379/14
• US Class Current: 370/253
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 43/106 using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 43/18 Protocol analysers
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A plurality of digital transmission network analyzers are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network. Each analyzer has its own internal clock for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at a each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis, and reporting to the controlling CPU. This analyzer intercommunication is done over a separate bus that interconnects all of the analyzers and the controlling CPU.

Claims

1. An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability, a facility for participating in the analysis with at least one other analyzer with which said analyzer is synchronized, for analysis at least two ports of a digital transmission network, said analyzer including:

a counter, the output of which is used to time stamp data packets received by said analyzer, the input of the counter being interconnectible with the input of the clock of said other analyzer;

a clock, the output of which is interconnectible with the input of the counter of said analyzer and to the input of the counter of said other analyzer; and

a clock control circuit for selectively interconnecting the clock of said analyzer to the counter of said analyzer and to the counter of said other analyzer, and for disabling the connection between the clock of said analyzer and the counter of said analyzer in response to a received clock-disable signal, thereby allowing the clock output of said other analyzer to substitute for the output of the clock of said analyzer having its counter connection disabled.

2. An analyzer as set forth in claim 1 further comprising a control computer for causing the issuance of clock-disable commands to operate the clock control circuit.

3. An analyzer according to claim 1 wherein said clock control circuit is also capable of sending to said other network analyzer a clock-disable command, whereby the clock output substitutes for the clock output of said other analyzer.

4. An analyzer according to claim 3 wherein there are a plurality of other analyzers and each other analyzer that receives a clock-disable command sends a clock-disable command to another of the other analyzers.

5. An analyzer according to claim 1 wherein said received clock-disable command is received from said other analyzer.

6. A digital transmission network analyzer system for analyzing networks with multiple ports at which each packet of data appears sequentially around a loop (12) of such ports, the analyzers of said system having data packet analyzing capability, each analyzer of said system having a facility for analyzing, with synchronization of the clocking between the analyzers, the analyzer system comprising:

a plurality of individual network analyzers, each having the capacity to store the header of a received packet of data, along with a time stamp representing when that packet arrived at the network analyzer, and each network analyzer also having a counter, responsive to received clock signals for indicating by its count the time elapsed since the counter was last reset, the output of the counter used to time stamp data packets received by the analyzer, each analyzer connected to a different port on the network;

a control computer, separate from the analyzers but linked to each analyzer, said computer being programmed to cause the counters of all analyzers to be reset simultaneously prior to the start of a test; and

a source of clock signals independent of the control computer and independent of at least one of the analyzers for advancing the counters of all of the analyzers in unison and in the same numerical direction.

7. A digital transmission network analyzer system according to claim 6 wherein:

said source of clock signals is a bit-rate clock source for clocking the transmission of bits throughout the network.

8. A digital transmission network analyzer system according to claim 7 wherein:

said source of clock signals is independent of all of the analyzers and of the control computer.

9. A digital transmission network analyzer system according to claim 8 wherein:

said bit-rate clock source is derived from a network master clock.

10. A digital transmission network analyzer system according to claim 6 wherein:

said source of clock signals is independent of the bit stream flowing in the network.

11. A digital transmission network analyzer system for analyzing networks with multiple ports at which each packet of data will appear, the analyzers of said system having data packet analyzing capability, each analyzer of said system having a facility for analyzing, with synchronization of the clocking between the analyzers, the analyzer system comprising:

a plurality of individual network analyzers, each having a counter, responsive to received clock signals for indicating by its count the time elapsed since the counter was last reset, the output of the counter used to time stamp data packets received by the analyzer, each analyzer connected to a different port on the network;

a control computer, separate from the analyzers but linked to each analyzer, said computer being programmed to cause the counters of all analyzers to be reset simultaneously prior to the start of a test; and

a source of clock signals independent of the control computer and independent of all but one of the analyzers for advancing the counters of all of the analyzers in unison and in the same numerical direction.

12. A digital transmission network analyzer system according to claim 11 wherein:

said source of clock signals is independent of the bit stream flowing in the network.