Method and system for a multi channel and search global position system signal processor

• US 5,535,237 A
• Filed: 02/04/1994
• Issued: 07/09/1996
• Est. Priority Date: 02/28/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Volpi, John P., Rekieta, David W., Scott, Hugh L., Lu, Chyi H., Pawlowski, George W., LaPadula, Leonard J. III, Stiles, Mitchel B.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US08/192,210
• Time in Patent Office: 886 Days
• Field of Search: 375/1, 375/200-210, 380/34, 342/352, 342/357, 455/314
• US Class Current: 375/130
• CPC Class Codes: G01S 19/21 Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

There is disclosed a multi channel GPS digital signal processor on a single IC. Each channel contains circuitry to process L1 or L2 P(Y) and C/A-code signals. In addition a search processor is included to achieve fast signal acquisition. Low power adder/accumulators have been designed to provide for a high precision digital oscillator whose output is synchronous to a high speed clock. The IC contains a full low power null detector and eight correlators to aid in signal acquisition.

Claims

1. A digital signal processing (DSP) circuit for use in a global positioning system (GPS) receiver, said DSP circuit comprising, on a single integrated circuit (IC):

Y-code generator circuitry; and

at least one signal processing channel, said channel including circuitry means for processing at least one of a valid P-code signal and Y-code signal from at least one satellite of said GPS.

2. The circuit set forth in claim 1 wherein said DSP includes circuitry for processing C/A code.

3. The circuit set forth in claim 2 wherein said DSP includes:

circuitry for tracking C/A and P-code simultaneously.

4. The circuit set forth in claim 1 wherein said DSP includes circuitry for processing P-code or Y-code selectively.

5. The circuit set forth in claim 4 wherein said DSP includes circuitry for processing multiple channels.

6. The circuitry set forth in claim 5 wherein said Y-code on any said channel is generated by a single Y-code generator common to all said multiple channels.

7. The circuitry set forth in claim 1 wherein said DSP includes circuitry for processing multiple channels.

8. The circuitry set forth in claim 7 wherein said DSP includes:

a noise meter per channel for aiding in said acquiring or tracking of signal.

9. The circuitry set forth in claim 7 wherein said DSP includes circuitry for allowing one channel to generate a test signal for use by other channels.

10. The circuitry set forth in claim 1 further comprising:

circuitry for selectively processing L1 or L2 signals.

11. The circuitry set forth in claim 1 wherein said DSP includes:

circuitry for establishing programmable integration periods for signal correlation.

12. The circuitry set forth in claim 1 wherein said DSP includes a noise meter for aiding in said acquiring or tracking of signal.

13. The circuitry set forth in claim 1 wherein said DSP includes circuitry for supporting full null zone signal inputs.

14. The circuitry set forth in claim 1 wherein said DSP includes a search processor for fast signal acquisition.

15. The circuitry set forth in claim 14 wherein said search processor includes a fourier transform function.

16. The circuitry set forth in claim 15 wherein said search processor further includes circuitry to interpolate new frequency bins between the frequency bins of said fourier transform function.

17. The circuitry set forth in claim 14 wherein said search processor includes a Tong detection algorithm.

18. The circuitry set forth in claim 17 wherein said search processor further includes frequency bin mask bits which exclude certain frequency bins of said fourier transform from being considered in said Tong detection algorithm.

19. The circuitry set forth in claim 17 wherein said search processor further includes correlator mask bits which exclude certain code states from being considered in said Tong detection algorithm.

20. The circuitry set forth in claim 14 wherein said search processor includes:

a mush counter for controlling the time that said digital signal processing circuitry attempts to acquire any particular signal.

21. The circuitry set forth in claim 14 wherein said search processor includes:

a mush counter for providing an indication of either a bad signal or a bad search threshold.

22. The circuitry set forth in claim 14 wherein said search processor further includes a hit counter for aiding in the determination of the adequacy of a search threshold.

23. The circuitry set forth in claim 14 wherein said search processor further includes a threshold calculator which autonomously adjusts for noise level.

24. The circuitry set forth in claim 23 wherein said threshold calculator further includes the calculation of a second threshold for the interpolated frequency bins which is the square root of 2 greater than the regular threshold.

25. The circuitry set forth in claim 14 wherein said search processor utilizes a Robertson approximation to generate correlation envelopes.

26. The circuitry set forth in claim 1 wherein said DSP further includes a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock which mostly runs at a significantly lower frequency for reduced power dissipation.

27. The circuitry set forth in claim 26 wherein said digital oscillator for carrier generation includes circuitry for selective one or two bit carrier generation.

28. The circuitry set forth in claim 1 wherein said DSP further includes:

an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including;

pulse injectors operating in conjunction with a ripple counter for reduced power dissipation and gate count.

29. The circuitry set forth in claim 1 wherein said DSP further includes:

a correlator configuration including ripple counters for predetection integration bias accumulation; and

an adder for subtraction of said bias.

30. The circuitry set forth in claim 29 wherein said correlator configuration supports adjacent correlator presumming.

31. The circuitry set forth in claim 29 wherein said correlator configuration supports full null zone operation.

32. A device for use in GPS receivers for processing of multiple digitized satellite signals, said device comprising, on a single application specific integrated circuit (ASIC):

Y-code generator circuitry;

multiple P(Y) and C/A-code channel means for processing said multiple digitized satellite signals; and

a search processor for fast signal acquisition.

33. The device set forth in claim 32 further including:

circuitry for tracking said C/A and P(Y)-code simultaneously.

34. The device set forth in claim 32 further including:

circuitry for processing P-code or Y-code selectively.

35. The device set forth in claim 32 wherein said Y-code is generated by a single Y-code generator common to all said multiple channels.

36. The device set forth in claim 32 further including:

circuitry for selectively processing L1 or L2 signals.

37. The device set forth in claim 32 further including:

circuitry for establishing programmable integration periods for signal correlation.

38. The device set forth in claim 32 further including:

a noise meter for aiding in acquiring or tracking said signals.

39. The device set forth in claim 32 further including:

circuitry for supporting full null zone signal inputs.

40. The device set forth in claim 32 wherein said search processor includes a fourier transform function implementation circuit.

41. The device set forth in claim 40 wherein said search processor further includes:

circuitry to interpolate new frequency bins between the frequency bins of said fourier transform.

42. The device set forth in claim 32 wherein said search processor includes a Tong detection algorithm implementation circuit.

43. The device set forth in claim 42 wherein said search processor further includes:

first circuitry means for providing frequency bin mask bits which exclude certain frequency bins from being considered in said Tong detection algorithm implementation circuit.

44. The device set forth in claim 42 wherein said search processor further includes:

second circuitry means for providing correlator mask bits which exclude certain code states from being considered in said Tong detection algorithm implementation circuit.

45. The device set forth in claim 32 wherein said search processor includes:

a mush counter for controlling the time that said processor attempts to acquire any particular signal.

46. The device set forth in claim 32 wherein said search processor includes:

a mush counter for providing an indication of either a bad signal or a bad search threshold.

47. The device set forth in claim 32 wherein said search processor further includes:

a hit counter means for aiding in the determination of the adequacy of a search threshold.

48. The device set forth in claim 32 wherein said search processor further includes:

a threshold calculator which autonomously adjusts for noise level.

49. The device set forth in claim 48 wherein said threshold calculator further includes:

circuitry for calculating a second threshold for the interpolated frequency bins.

50. The device set forth in claim 32 wherein said search processor further includes:

circuitry for utilizing the Robertson approximation to generate correlation envelopes.

51. The device set forth in claim 32 further including:

a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock which mostly runs at a significantly lower frequency for reduced power dissipation.

52. The device set forth in claim 51 wherein said digital oscillator for carrier generation includes circuitry for selective one or two bit carrier generation.

53. The device set forth in claim 32 further including:

an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including;

pulse injectors operating in conjunction with a ripple counter for reducing power and gate count.

54. The device set forth in claim 32 further including:

a correlator configuration using ripple counters for predetection integration and bias accumulation; and

an adder for subtraction of said bias.

55. The device set forth in claim 54 wherein said correlator configuration supports adjacent correlator presumming.

56. The device set forth in claim 54 wherein said correlator configuration supports full null zone operation.

57. The device set forth in claim 32 further including:

third circuitry means for causing one channel to generate a test signal for use by other channels.

58. The device set forth in claim 32 further including:

circuitry for establishing variable integration periods for signal predetection integration.

59. A device for tracking and acquiring global positioning system (GPS) signals from multiple satellites, said device comprising, on a single integrated circuit:

Y-code generator circuitry;

two P(Y) and C/A-code channels;

a search processor for fast signal acquisition;

support circuitry means for processing null zone signals;

said channels each comprising;

a carrier generator;

a code clock generator;

a P-code generator;

a C/A-code generator;

eight predetection integration accumulators; and

a noise meter;

said search processor comprising;

a discrete fourier transform circuit;

first circuitry means for performing frequency bin interpolation;

second circuitry means for implementing a Robertson approximation for envelope calculation;

third circuitry means for implementing a Tong detection algorithm to determine if signal is present;

a threshold calculator which uses measurements from said noise meter;

fourth circuitry means for calculating a second search threshold for the interpolated frequency bins;

fifth circuitry means for advancing or retarding code state as required during search;

a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and

a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.

60. The device set forth in claim 59 wherein said predetection accumulators include:

circuitry for performing adjacent correlator presumming for removal of signal to noise ratio holes between code states;

a circuit configuration using ripple counters so as to minimize power consumption and gate count; and

a circuit configuration using ripple counters and pulse injectors to minimize power consumption of high frequency sample accumulation.

61. The device set forth in claim 59 wherein said carrier and code clock generators include:

a digital oscillator circuit architecture which generates a carrier or code clock output synchronous to a high frequency clock but mostly runs at a low frequency to minimize power consumption; and

a low frequency adder/accumulator using ripple counters and pulse injectors which reduce gate count.

62. The device set forth in claim 59 further including:

a circuit for converting P-code to Y-code which supports both channels simultaneously.

63. The device set forth in claim 59 further including:

circuitry for tracking C/A and P-code simultaneously.

64. The device set forth in claim 59 further including:

circuitry for establishing programmable integration periods for signal correlation.

65. The device set forth in claim 59 wherein said search processor further includes:

sixth circuitry means for providing frequency bin mask bits which exclude certain frequency bins from being considered in said Tong detection algorithm.

66. The device set forth in claim 59 wherein said search processor further includes:

seventh circuitry means for providing correlator mask bits which exclude certain code states from being considered in said Tong detection algorithm.

67. The device set forth in claim 59 further including:

correlator configuration circuitry using ripple counters for predetection integration and bias accumulation; and

an adder for subtraction of said bias.

68. The device set forth in claim 67 wherein said correlator configuration circuitry provides adjacent correlator presumming.

69. The device set forth in claim 68, wherein said correlator configuration circuitry provides full null zone operation.

70. The device set forth in claim 59 further including:

eighth circuitry means for causing one channel to generate a test signal for use by other channels.

71. A device for use in GPS receivers for processing of multiple digitized satellite signals, said device comprising, on a single integrated circuit:

multiple P(Y) and C/A-code channel means for processing said multiple digitized satellite signals; and

a search processor for fast signal acquisition, including means for simultaneously searching a plurality of frequency bins in each of said multiple channel means.

72. The device set forth in claim 71 further including:

circuitry for selectively processing L1 or L2 signals.

73. A device for tracking and acquiring global positioning system (GPS) signals from multiple satellites, said device comprising, on a single integrated circuit:

two P(Y) and C/A-code channels;

a search processor for fast signal acquisition;

support circuitry means for processing null zone signals;

said channels each comprising;

a carrier generator;

a code clock generator;

a P-code generator;

a C/A-code generator;

eight predetection integration accumulators; and

a noise meter;

said search processor comprising;

a discrete fourier transform circuit;

first circuitry means for performing frequency bin interpolation;

second circuitry means for implementing a Robertson approximation for envelope calculation;

third circuitry means for implementing a Tong detection algorithm to determine if signal is present;

a threshold calculator which uses measurements from said noise meter;

fourth circuitry means for calculating a second search threshold for the interpolated frequency bins;

fifth circuitry means for advancing or retarding code state as required during search;

a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and

a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.