Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed

• US 5,535,345 A
• Filed: 05/12/1994
• Issued: 07/09/1996
• Est. Priority Date: 05/12/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Malhotra, Ajay, Fisch, Matthew A., Brayton, James M.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US08/241,964
• Time in Patent Office: 789 Days
• Field of Search: 395/287, 395/292, 395/288, 395/308, 395/307, 395/467, 395/436, 395/309, 395/306
• US Class Current: 710/305
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

In accordance with the preferred embodiment of the present invention, a bus interface unit of a microprocessor is provided with a Micro Request Sequencer (EBMRS) disposed between a bus scheduling queue (EBBQ) and external bus control logic (EBCTL). Under normal bus request traffic, the EBMRS is effectively transparent and allows normal communication between the EBCTL and the EBBQ. However, for misaligned bus transactions, which comprise memory accesses that cross a bus width boundary, the EBMRS intercepts such transactions for special sequencing, while blocking any further requests from the EBBQ. The EBMRS separates each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus. It then issues the first split request to the EBCTL for processing on the external bus. External bus agents involved with processing of the split requests then return first response information regarding the completion of the first split request. If the first response information indicates that the first split request will complete without being deferred or retried, the EBMRS issues the second split request to the EBCTL for processing on the external bus. Upon the receipt of second response information for the second split request indicating that the second split request is guaranteed to complete without being deferred or retried, the EBMRS then issues any further transaction requests received from the EBBQ without jeopardizing the order dependency of the split requests or subsequent bus transaction requests buffered in the EBBQ.

Claims

1. In a microprocessor having an associated bus interface unit with control logic for coupling the microprocessor to an external bus and processing external bus transaction requests on the external bus, a method is provided for sequencing misaligned bus transaction requests on the external bus, each of said misaligned bus transaction request forming a memory access crossing a data bus width boundary of the external bus, the method comprising the steps of:

said bus interface unit of said microprocessor separating each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus;

issuing the first split request to the control logic of the bus interface unit for processing of the first split request on the external bus;

determining whether a global observation has been issued for said first split request;

in response to said global observation of said first split request issuing the second split request to the control logic of the bus interface unit for processing of the second split request on the external bus;

determining whether a global observation has been issued for said second split request; and

in response to said global observation of said second split request, completing processing of the second split request on the external bus in order with respect to issuance of the first split request.

2. The method of claim 1, wherein the bus interface unit further comprises a bus queue for buffering and issuing requests and a transaction request sequencer for sequencing the requests received from the bus queue to the control logic, and before the step of separating each misaligned bus transaction request into at least first and second split transaction requests, the method further comprises the steps of:

transmitting external bus transaction requests from a requesting unit of the microprocessor to the bus queue;

issuing the bus transaction requests from the bus queue to the transaction request sequencer; and

identifying bus transaction requests which cross a data bus width boundary of the external bus as misaligned bus transaction requests.

3. The method of claim 2, wherein the steps of determining whether the global observation of said first split request has been issued and issuing the second split request to the control logic of the bus interface unit in response to said global observation is performed by the steps of:

transmitting said global observation from bus agents coupled to the external bus to the control logic of the bus interface unit, the global observation indicating whether the first split transaction request will complete without being deferred or retried;

transmitting a first completion guarantee signal from the control logic to the sequencer when the first response information indicates that the first split transaction request is guaranteed to complete without being deferred or retried; and

issuing the second split request from the sequencer to the control logic of the bus interface unit for processing of the second split request on the external bus when the first completion guarantee signal for the first split request is received by the sequencer from the control logic.

4. The method of claim 2, wherein the steps of determining whether the global observation of said second split request has been issued and completing processing of the second split request on the external bus in order with respect to issuance of the first split request in response to said global observation of said second split request is performed by the steps of:

transmitting said global observation from bus agents coupled to the external bus to the control logic of the bus interface unit, the global observation indicating whether the second split transaction request is guaranteed to complete without being deferred or retried;

transmitting a second completion guarantee signal from the control logic to the sequencer when the second response information indicates that the second split transaction request is guaranteed to complete without being deferred or retried; and

completing processing of the second split request on the external bus when the second completion guarantee signal for the second split request is received by the sequencer from the control logic.

5. The method of claim 2, wherein the step of identifying bus transaction requests which cross a data bus width boundary of the external bus as misaligned bus transaction requests is performed by one of the bus queue and the sequencer.

6. The method of claim 1, wherein the method further comprises the step of canceling the misaligned bus transaction request upon the occurrence of a hard error.

7. In a microprocessor having an associated bus interface unit with control logic for transferring data between the microprocessor and external bus agents via an external bus, a method is provided for sequencing misaligned bus transaction requests on the external bus, each said misaligned bus transaction request forming a memory access crossing a data bus width boundary of the external bus, the method comprising the steps of:

transmitting external bus transaction requests generated by the microprocessor to the bus interface unit;

determining whether the data to be transferred in each external bus transaction request will cross a data bus width boundary of the external bus;

said bus interface of said microprocessor separating each external bus transaction request denoted as a misaligned bus transaction request into at least first and second split transaction requests when the data to be transferred in the external bus transaction request will cross a data bus width boundary of the external bus, with each split request forming a memory access that does not cross a data bus width boundary of the external bus;

issuing the first split request of each misaligned bus transaction request to the control logic of the bus interface unit;

transmitting request and address information corresponding the first split request from the control logic to the bus agent specified by the address information to effect a transfer of data between the microprocessor and the addressed bus agent;

transmitting a first global observation from the bus agents to the control logic of the bus interface unit;

issuing the second split request to the control logic of the bus interface unit when the first global observation transmitted from the bus agents is received by said control logic;

transmitting a second global observation from the bus agents to the control logic of the bus interface unit; and

completing processing of the second split request on the external bus in order with respect to issuance of the first split request when the second global observation is received by said control logic.

8. The method of claim 7, wherein for a misaligned bus transaction request comprising a bus lock transaction request of a sequence of locked transaction requests for which the external bus must be locked for exclusive use by the microprocessor in processing the sequence of locked transaction requests, the method further comprises the step of locking the external bus for exclusive use by the microprocessor upon issuance of the first split request of the misaligned bus lock transaction request to the control logic.

9. The method of claim 7, wherein for a misaligned bus transaction request comprising a bus unlock transaction request of a sequence of locked transaction requests for which the external bus must be locked for exclusive use by the microprocessor in processing of the sequence of locked transaction requests, the method further comprises the step of unlocking the external bus to enable use of the external bus by other bus agents when the second global observation for the second split request is received from the external bus agents.

10. The method of claim 7, wherein the method further comprises the step of canceling the misaligned bus transaction request upon the occurrence of a hard error.

11. In an out-of-order microprocessor comprising an instruction fetch unit, a data cache unit and an associated bus interface unit for transferring data between one of the instruction fetch unit and the data cache unit and external bus agents via an external bus, a method is provided for sequencing misaligned bus transaction requests on the external bus, each misaligned bus transaction request forming a memory access crossing a data bus width boundary of the external bus, the bus interface unit having control logic capable of processing external bus transaction requests in order of receipt from the instruction fetch unit and the data cache unit, the method comprising the steps of:

A) transmitting external bus transaction requests from one of the instruction fetch unit and the data cache unit to a bus queue of the bus interface unit for buffering of the bus transaction requests;

B) issuing the bus transaction requests from the bus queue to a transaction request sequencer of the bus interface unit;

C) identifying bus transaction requests which cross a data bus width boundary of the external bus as misaligned bus transaction requests;

D) separating each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus;

E) issuing the first split request of the misaligned bus transaction request from the sequencer to the control logic of the bus interface unit for processing of the first split request on the external bus;

F) transmitting first response information from the bus agents coupled to the external bus to the control logic of the bus interface unit, the first response information indicating at least whether the first split transaction request will complete without being deferred or retried;

G) transmitting a first completion guarantee signal from the control logic to the sequencer when the first response information indicates that the first split transaction request is guaranteed to complete without being deferred or retried;

H) issuing the second split request from the sequencer to the control logic of the bus interface unit for processing of the second split request on the external bus when a first completion guarantee signal for the first split request is received by the sequencer from the control logic;

I) transmitting second response information from the bus agents to the control logic of the bus interface unit, the second response information indicating at least whether the second split transaction request is guaranteed to complete without being deferred or retried;

J) transmitting a second completion guarantee signal from the control logic to the sequencer when the second response information indicates that the second split transaction request is guaranteed to complete without being deferred or retried; and

K) returning to step B) when the second completion guarantee signal for the second split request is received by the sequencer from the bus control logic.

12. The method of claim 11, wherein for a misaligned bus transaction request comprising a bus lock transaction request of a sequence of locked transaction requests for which the external bus must be locked for exclusive use by the microprocessor in processing the sequence of locked transaction requests, the method further comprises the step of locking the external bus for exclusive use by the microprocessor upon issuance of the first split request of the misaligned bus lock transaction request from the sequencer to the control logic.

13. The method of claim 11, wherein for a misaligned bus transaction request comprising a bus unlock transaction request of a sequence of locked transaction requests for which the external bus must be locked for exclusive use by the microprocessor in processing of the sequence of locked transaction requests, the method further comprises the step of unlocking the external bus to enable use of the external bus by other bus agents when the second response information for the second split request received from the external bus agents indicates that no errors have occurred in processing of the second split request.

14. The method of claim 11, wherein the step of identifying bus transaction requests which cross a data bus width boundary of the external bus as misaligned bus transaction requests is performed by one of the bus queue and the sequencer.

15. The method of claim 11, wherein the method further comprises the step of canceling the misaligned bus transaction request upon the occurrence of a hard error.

16. An apparatus for sequencing misaligned bus transaction requests between a microprocessor and external bus agents coupled together via an external bus, each said misaligned bus transaction request forming a memory access crossing a data bus width boundary of the external bus, the apparatus comprising:

a transaction request sequencer for receiving bus transaction requests from the microprocessor and identifying bus transaction requests which cross a data bus width boundary of the external bus as misaligned bus transaction requests, the sequencer separating each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus;

control logic for receiving bus transaction requests from the sequencer and processing bus transaction requests on the external bus; and

wherein in the case of a misaligned bus transaction request, the sequencer issues the first and second split requests in order to the control logic for driving of associated request and address information on the external bus to process the first and second requests, with the second split request being issued from the sequencer to the control logic only after receiving a first global observation for the first split request from external bus agents.

17. The apparatus of claim 16, wherein for a misaligned bus transaction request comprising a bus lock transaction request of a sequence of locked transaction requests for which the external bus must be locked for exclusive use by the microprocessor in processing the sequence of locked transaction requests, the external bus is locked for exclusive use by the microprocessor upon issuance of the first split request of the misaligned bus lock transaction request from the sequencer to the control logic.

18. The apparatus of claim 16, wherein for a misaligned bus transaction request comprising a bus unlock transaction request of a sequence of locked transaction requests for which the external bus must be locked for exclusive use by the microprocessor in processing of the sequence of locked transaction requests, the external bus is unlocked to enable use of the external bus by other bus agents when said second global observation for the second split request from the external bus agents is received by the control logic.

19. In a computer system having a microprocessor, an external bus for communicating with external bus agents comprising at least a memory means, and a bus interface unit having control logic for transferring data between the microprocessor and the external bus agents, an apparatus is provided for sequencing misaligned bus transaction requests between the microprocessor and the external bus agents, each said misaligned bus transaction request forming a memory access crossing a data bus width boundary of the external bus, the apparatus comprising:

a transaction request sequencer for receiving bus transaction requests from the microprocessor and identifying bus transaction requests which cross a data bus width boundary of the external bus as misaligned bus transaction requests, the sequencer separating each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus;

control logic for processing bus transaction requests issued from the sequencer on the external bus; and

wherein in the case of a misaligned bus transaction request, the sequencer issues the first and second split requests in order to the control logic for driving of associated request and address information on the external bus to process the first and second requests, with the second split request being issued from the sequencer to the control logic only after receiving a first global observation for the first split request from external bus agents.

20. The apparatus of claim 19, wherein the microprocessor comprises an out-of-order microprocessor having an execution unit for executing instructions out-of-order, a dispatch buffer for temporarily storing microinstructions until the execution unit is available and a reorder buffer for buffering instructions and corresponding execution results after instruction execution.