Cache memory control circuit and method for controlling reading and writing requests

• US 5,535,358 A
• Filed: 12/27/1994
• Issued: 07/09/1996
• Est. Priority Date: 12/27/1993
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kiyohara, Tokuzo, Kimura, Kozo
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/364,277
• Time in Patent Office: 560 Days
• Field of Search: 395/445, 395/451, 395/460, 395/467, 395/468, 395/471, 395/472, 395/483, 395/494, 395/496, 395/495, 395/375
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

In cases where a remarked unit of tag addresses set in effective or access state is not registered in a tag section when a reading request is input, an external access is performed, and the remarked unit of tag addresses and other units of tag addresses respectively set in the access state are prepared in a tag entry preparing unit. In cases where a writing request is input to write a piece of updated word data in a remarked unit of data addresses corresponding to the remarked unit of tag addresses before the external access is finished, the state of the remarked tag entry prepared is changed to the effective state, and the updated word data is written in the remarked unit of data addresses of a data storing unit. Because the remarked unit of tag addresses is set in the effective state, the updated word data written in the remarked unit of data addresses is not replaced with a piece of external word data obtained according to the external access when the external access is finished. In cases where any writing request is not input until the external access is finished, the external word data is written in the remarked unit of data addresses, and the state of the remarked unit of tag addresses is changed to the effective state to replace the external word data with a piece of updated word data relating to a following writing request. Therefore, the writing and reading requests can be performed without delaying the writing request.

Claims

1. A cache memory control circuit, comprising:

data storing means for storing pieces of word data in each of a plurality of data entries, N pieces of word data being stored in each of the data entries, each of the word data being stored in M data addresses, and a set of M data addresses for a piece of word data functioning as an administrative unit;

tag means for registering a plurality of tag addresses in a plurality of tag entries and a plurality of entry states respectively determined for a unit of M tag addresses, M×

N tag addresses being registered in each of the tag entries, N entry states being determined in each of the tag entries, the tag entries corresponding to the data entries in one-to-one correspondence, the tag addresses corresponding to one of the data addresses in one-to-one correspondence, the entry states being classified into an effective state, an invalid state and an access state, the effective state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is effective, the invalid state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is invalid, and the access state for a unit of M tag addresses indicating that an external access for searching for a piece of external word data expected to be stored in M data addresses corresponding to the unit of M tag addresses is under performance;

hit judging means for judging whether an entry state registered in the tag means is set in the effective state or the invalid state, outputting an external access request to request an external access for the purpose of obtaining N pieces of external word data to be stored in a first remarked data entry of the data storing means corresponding to a first remarked tag entry of the tag means which is designated by a first input tag address relating to a reading request in cases where it is judged that an entry state of a first remarked unit of M tag addresses represented by the first input tag address is set in the invalid state, outputting a first hit signal in cases where it is judged that an entry state of the first remarked unit of M tag addresses represented by the first input tag address is set in the effective state, and outputting a second hit signal in cases where it is judged that an entry state of a second remarked unit of M tag addresses represented by a second input tag address relating to a writing request is set in the effective state;

tag entry preparing means for preparing the first remarked tag entry in which the first remarked unit of M tag addresses and other three remarked units of M tag addresses are respectively set in the access state in the tag means in cases where it is judged by the hit judging means that the entry state of the first remarked unit of M tag addresses represented by the first input tag address is set in the invalid state;

access state detecting means for detecting whether or not the second remarked unit of M tag addresses is set in the access state in cases where it is judged by the hit judging means that the entry state of the second remarked unit of M tag addresses is not set in the effective state, and detecting whether or not the first remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state in cases where the external access requested by the hit judging means is finished, the second remarked unit of M tag addresses being set in the access state in cases where the second remarked unit of M tag addresses agrees with the first remarked unit of M tag addresses or the other three remarked units of M tag addresses registered in the first remarked tag entry on condition that the external access requested by the hit judging means is not finished, and the first remarked unit of M tag addresses prepared by the tag entry preparing means being maintained in the access state in cases where the external access requested by the hit judging means is not finished;

tag writing-in control means for changing the entry state of the second remarked unit of M tag addresses from the access state to the effective state in cases where it is judged by the access state detecting means that the second remarked unit of M tag addresses is set in the access state, and changing the entry state of the first remarked unit of M tag addresses from the access state to the effective state in cases where it is judged by the access state detecting means that the first remarked unit of M tag addresses is set in the access state on condition that the external access requested by the hit judging means is finished;

data writing operation control means for writing the N external word data obtained according to the external access request of the hit judging means in the first remarked data entry of the data storing means in cases where it is detected by the access state detecting means that each of the remarked units of M tag addresses in the first remarked tag entry prepared by the tag entry preparing means is set in the access state, writing a piece of first updated word data in a second remarked unit of data addresses of the data storing means corresponding to the second remarked unit of M tag addresses in cases where the second hit signal output from the hit judging means is received, and writing a piece of second updated word data in a second remarked unit of M data addresses of the data storing means corresponding to the second remarked unit of M tag addresses in cases where it is judged by the access state detecting means that the second remarked unit of tag addresses is set in the access state; and

data reading operation control means for reading one of the N external word data which is obtained according to the external access request of the hit judging means and is stored in a first remarked unit of M data addresses of the data storing means corresponding to the first remarked unit of M tag addresses in cases where the N external word data are written in the first remarked data entry of the data storing means by the data writing operation control means, and reading a piece of required word data stored in a first remarked unit of M data addresses of the data storing means corresponding to the first remarked unit of M tag addresses in cases where the first hit signal output from the hit judging means is received.

2. A cache memory control circuit according to claim 1 in which the second remarked unit of M tag addresses is set in the invalid state under the control of the tag writing-in control means on condition that the second updated word data expected to be written in the second remarked unit of M data addresses of the data storing means under the control of the data writing operation control means has a size smaller than that of the second remarked unit of M data addresses functioning as the administrative unit in cases where it is judged by the access state detecting means that the second remarked unit of M tag addresses is set in the access state, and the second updated word data is not written in the second remarked unit of M data addresses corresponding to the second remarked unit of M tag addresses set in the invalid state under the control of the data writing operation control means.

3. A cache memory control circuit according to claim 1 in which a writing operation of the second updated word data in the second remarked unit of M data addresses of the data storing means is delayed until the external access requested by the hit judging means is finished on condition that the second updated word data has a size smaller than that of the second remarked unit of M data addresses functioning as the administrative unit in cases where it is judged by the access state detecting means that the second remarked unit of M tag addresses is set in the access state.

4. A cache memory control circuit according to claim 1 in which the first remarked unit of M tag addresses is set in the invalid state under the control of the tag writing-in control means in cases where an invalidating request for invalidating the entry state of the first remarked unit of M tag addresses is sent to the tag writing-in control means until the external access requested by the hit judging means is finished, and a piece of external word data obtained by the external access is not written in the first remarked unit of M data addresses corresponding to the first remarked unit of M tag addresses set in the invalid state.

5. A cache memory control circuit, comprising:

data storing means for storing pieces of word data in each of a plurality of data entries, N pieces of word data being stored in each of the data entries, each of the word data being stored in M data addresses, and a set of M data addresses for a piece of word data functioning as an administrative unit;

tag means for registering a plurality of tag addresses in a plurality of tag entries and a plurality of entry states respectively determined for a unit of M tag addresses, M×

N tag addresses being registered in each of the tag entries, N entry states being determined in each of the tag entries, the tag entries corresponding to the data entries in one-to-one correspondence, the tag addresses corresponding to one of the data addresses in one-to-one correspondence, the entry states being classified into an effective state, an invalid state and an access state, the effective state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is effective, the invalid state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is invalid, and the access state for a unit of M tag addresses indicating that an external access for searching for a piece of external word data expected to be stored in M data addresses corresponding to the unit of M tag addresses is under performance;

hit judging means for judging whether or not a unit of M tag addresses set in the effective state is registered in the tag means, and outputting an external access request to request an external access in cases where it is judged that a first remarked unit of M tag addresses which is set in the effective state and is represented by a first input tag address relating to a first writing request for requesting to store a piece of first updated word data in a first remarked unit of M data addresses corresponding to the first remarked unit of tag addresses is not registered in the tag means;

tag entry preparing means for preparing a tag line, in which the first remarked unit of tag addresses and a second remarked unit of tag addresses respectively set in the access state are included, in the tag means to prepare a data line in which the first remarked unit of M data addresses and a second remarked unit of M data addresses corresponding to the second remarked unit of M tag addresses are registered in the data storing means in cases where it is judged by the hit judging means that the first remarked unit of M tag addresses set in the effective state is not registered in the tag means, a piece of external word data to be stored in the second remarked unit of data addresses being searched according to the external access requested by the hit judging means;

access state detecting means for detecting whether or not the second remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state in cases where it is judged by the hit judging means that the second remarked unit of M tag addresses which is set in the effective state and is represented by a second input tag address relating to a second writing request for requesting to store a piece of second updated word data in the second remarked unit of M data addresses is not registered in the tag means, and detecting whether or not the second remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state in cases where the external access requested by the hit judging means is finished;

tag writing-in control means for changing the entry state of the first remarked unit of M tag addresses from the access state to the effective state in cases where the tag line is prepared by the tag entry preparing means, changing the entry state of the second remarked unit of M tag addresses from the access state to the effective state to forbid a writing operation of the external word data in the second remarked unit of M data addresses set in the effective state in cases where it is detected by the access state detecting means according to the second writing request that the second remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state, and changing the entry state of the second remarked unit of M tag addresses from the access state to the effective state in cases where it is detected by the access state detecting means that the second remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state on condition that the external access requested by the hit judging means is finished; and

data writing operation control means for writing the first updated word data in the first remarked unit of M data addresses of the data line prepared by the tag entry preparing means, writing the second updated word data in the second remarked unit of M data addresses of the data line prepared by the tag entry preparing means in cases where it is detected by the access state detecting means according to the second writing request that the second remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state, and writing the external word data in the second remarked unit of M data addresses of the data line prepared by the tag entry preparing means in cases where it is detected by the access state detecting means that the second remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state on condition that the external access requested by the hit judging means is finished.

6. A cache memory control circuit according to claim 5 in which the first remarked unit of M tag addresses is set in the invalid state under the control of the tag writing-in control means on condition that the first updated word data expected to be written in the first remarked unit of M data addresses of the data storing means under the control of the data writing operation control means has a size smaller than that of the first unit of M data addresses functioning as the administrative unit in cases where it is judged by the access state detecting means that the first remarked unit of M tag addresses is set in the access state, and the first updated word data is not written in the first remarked unit of M data addresses corresponding to the first remarked unit of M tag addresses set in the invalid state under the control of the data writing operation control means.

7. A cache memory control circuit according to claim 5 in which a writing operation of the second updated word data in the second remarked unit of M data addresses of the data storing means is delayed until the external access requested by the hit judging means is finished on condition that the second updated word data has a size smaller than that of the second unit of M data addresses functioning as the administrative unit in cases where it is judged by the access state detecting means that the second remarked unit of M tag addresses is set in the access state.

8. A cache memory control circuit according to claim 5 in which the second remarked unit of M tag addresses is set in the invalid state under the control of the tag writing-in control means in cases where an invalidating request for invalidating the second remarked unit of M tag addresses is sent to the tag writing-in control means until the external access requested by the hit judging means is finished, and the external word data obtained by the external access is not written in the second remarked unit of M data addresses corresponding to the second remarked unit of M tag addresses set in the invalid state.

9. A cache memory control circuit, comprising:

data storing means for storing pieces of word data in each of a plurality of data entries, N pieces of word data being stored in each of the data entries, each of the word data being stored in M data addresses, and a set of M data addresses for a piece of word data functioning as an administrative unit;

tag means for registering a plurality of tag addresses in a plurality of tag entries and a plurality of entry states respectively determined for a unit of M tag addresses, M×

N tag addresses being registered in each of the tag entries, N entry states being determined in each of the tag entries, the tag entries corresponding to the data entries in one-to-one correspondence, the tag addresses corresponding to one of the data addresses in one-to-one correspondence, the entry states being classified into an effective state, an invalid state and an access state, the effective state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is effective, the invalid state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is invalid, and the access state for a unit of M tag addresses indicating that an external access for searching for a piece of external word data expected to be stored in M data addresses corresponding to the unit of M tag addresses is under performance;

hit judging means for judging whether an entry state registered in the tag means is set in the effective state or the invalid state, outputting an external access request to request an external access for the purpose of obtaining N pieces of external word data to be stored in a first remarked data entry of the data storing means corresponding to a first remarked tag entry of the tag means which is designated by a first input tag address relating to a reading request in cases where it is judged that an entry state of a first remarked unit of M tag addresses represented by the first input tag address is set in the invalid state, outputting a first hit signal in cases where it is judged that an entry state of the first remarked unit of M tag addresses represented by the first input tag address is set in the effective state, outputting a second hit signal in cases where it is judged that an entry state of a second remarked unit of M tag addresses represented by a second input tag address relating to a writing request is set in the effective state, and judging whether or not a bus monitoring unit of M tag addresses represented by a bus monitoring address input to the hit judging means is registered in the tag means, the bus monitoring address being input to the hit judging means in cases where the bus monitoring address passing through an external bus is monitored to detect the renewal of a piece of external data stored in a bus monitoring external region of an external main memory corresponding to the bus monitoring unit of M tag addresses;

tag entry preparing means for preparing the first remarked tag entry in which the first remarked unit of M tag addresses and other three remarked units of M tag addresses are respectively set in the access state in the tag means in cases where it is judged by the hit judging means that the entry state of the first remarked unit of M tag addresses represented by the first input tag address is set in the invalid state;

access state detecting means for detecting whether or not the second remarked unit of M tag addresses is set in the access state in cases where it is judged by the hit judging means that the entry state of the second remarked unit of M tag addresses is not set in the effective state, and detecting whether or not the first remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state in cases where the external access requested by the hit judging means is finished, the second remarked unit of M tag addresses being set in the access state in cases where the second remarked unit of M tag addresses agrees with the first remarked unit of M tag addresses or the other three remarked units of M tag addresses registered in the first remarked tag entry on condition that the external access requested by the hit judging means is not finished, and the first remarked unit of M tag addresses prepared by the tag entry preparing means being maintained in the access state in cases where the external access requested by the hit judging means is not finished;

tag writing-in control means for changing the entry state of the second remarked unit of M tag addresses from the access state to the effective state in cases where it is judged by the access state detecting means that the second remarked unit of M tag addresses is set in the access state, changing the entry state of the first remarked unit of M tag addresses from the access state to the effective state in cases where it is judged by the access state detecting means that the first remarked unit of M tag addresses is set in the access state on condition that the external access requested by the hit judging means is finished, and changing the entry state of the second remarked unit of M tag addresses changed to the effective state to the access state in cases where it is judged by the hit judging means that the bus monitoring unit of M tag addresses represented by the bus monitoring address input to the hit judging means is registered in the tag means on condition that the bus monitoring unit of M tag addresses agrees with the second remarked unit of M tag addresses registered in the tag means;

data writing operation control means for writing the external word data obtained according to the external access request of the hit judging means in the first remarked unit of M data addresses of the data storing means in cases where it is detected by the access state detecting means that the first remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state, writing a piece of first updated word data in a second remarked unit of M data addresses of the data storing means corresponding to the second remarked unit of M tag addresses in cases where the second hit signal output from the hit judging means is received, and writing a piece of second updated word data in a second remarked unit of M data addresses of the data storing means corresponding to the second remarked unit of M tag addresses in cases where it is judged by the access state detecting means that the second remarked tag entry is set in the access state, the external word data being written in the second remarked unit of M data addresses to replace the second updated word data written in the second remarked unit of M data addresses with the external word data in cases where the bus monitoring unit of M tag addresses, the first remarked unit of M tag addresses and the second remarked unit of M tag addresses agree with each other; and

data reading operation control means for reading the external word data obtained according to the external access request of the hit judging means in cases where the external word data is written in the first remarked unit of M data addresses of the data storing means by the data writing operation control means, and reading a piece of required word data stored in a first remarked data entry of the data storing means corresponding to the first remarked unit of M tag addresses in cases where the first hit signal output from the hit judging means is received.

10. A cache memory control circuit, comprising:

data storing means for storing pieces of word data in each of a plurality of data entries, N pieces of word data being stored in each of the data entries, each of the word data being stored in M data addresses, and a set of M data addresses for a piece of word data functioning as an administrative unit;

tag means for registering a plurality of tag addresses in a plurality of tag entries and a plurality of entry states respectively determined for a unit of M tag addresses, M×

N tag addresses being registered in each of the tag entries, N entry states being determined in each of the tag entries, the tag entries corresponding to the data entries in one-to-one correspondence, the tag addresses corresponding to one of the data addresses in one-to-one correspondence, the entry states being classified into an effective state, an invalid state and an access state, the effective state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is effective, the invalid state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is invalid, and the access state for a unit of M tag addresses indicating that an external access for searching for a piece of external word data expected to be stored in M data addresses corresponding to the unit of M tag addresses is under performance;

hit judging means for judging whether an entry state registered in the tag means is set in the effective state or the invalid state, outputting an external access request to request an external access for the purpose of obtaining N pieces of external word data to be stored in a first remarked data entry of the data storing means corresponding to a first remarked tag entry of the tag means which is designated by a first input tag address relating to a reading request in cases where it is judged that an entry state of a first remarked unit of M tag addresses represented by the first input tag address is set in the invalid state, outputting a first hit signal in cases where it is judged that an entry state of the first remarked unit of M tag addresses represented by the first input tag address is set in the effective state, outputting a second hit signal in cases where it is judged that an entry state of a second remarked unit of M tag addresses represented by a second input tag address relating to a writing request is set in the effective state, and judging whether or not a bus monitoring unit of M tag addresses represented by a bus monitoring address input to the hit judging means is registered in the tag means, the bus monitoring address being input to the hit judging means in cases where the bus monitoring address passing through an external bus is monitored to detect the renewal of a piece of external data stored in a bus monitoring external region of an external main memory corresponding to the bus monitoring unit of M tag addresses;

tag entry preparing means for preparing the first remarked tag entry in which the first remarked unit of M tag addresses and other three remarked units of M tag addresses are respectively set in the access state in the tag means in cases where it is judged by the hit judging means that the entry state of the first remarked unit of M tag addresses represented by the first input tag address is set in the invalid state;

access state detecting means for detecting whether or not the second remarked unit of M tag addresses is set in the access state in cases where it is judged by the hit judging means that the entry state of the second remarked unit of M tag addresses is not set in the effective state, and detecting whether or not the first remarked unit of M tag addresses prepared by the tag entry preparing means is set in the access state in cases where the external access requested by the hit judging means is finished, the second remarked unit of M tag addresses being set in the access state in cases where the second remarked unit of M tag addresses agrees with the first remarked unit of M tag addresses or the other three remarked units of M tag addresses registered in the first remarked tag entry on condition that the external access requested by the hit judging means is not finished, and the first remarked unit of M tag addresses prepared by the tag entry preparing means being maintained in the access state in cases where the external access requested by the hit judging means is not finished;

tag writing-in control means for changing the entry state of the second remarked unit of M tag addresses from the access state to the effective state in cases where it is judged by the access state detecting means that the second remarked unit of M tag addresses is set in the access state on condition that it is judged by the input judging means that the bus monitoring unit of M tag addresses does not agree with the second remarked unit of M tag addresses, and changing the entry state of the first remarked unit of M tag addresses from the access state to the effective state in cases where it is judged by the access state detecting means that the first remarked unit of M tag addresses is set in the access state on condition that the external access requested by the hit judging means is finished;

data writing operation control means for writing the N external word data obtained according to the external access request of the hit judging means in the first remarked data entry of the data storing means in cases where it is detected by the access state detecting means that each of the remarked units of M tag addresses in the first remarked tag entry prepared by the tag entry preparing means is set in the access state, writing a piece of first updated word data in a second remarked unit of data addresses of the data storing means corresponding to the second remarked unit of M tag addresses in cases where the second hit signal output from the hit judging means is received, and writing a piece of second updated word data in a second remarked unit of M data addresses of the data storing means corresponding to the second remarked unit of M tag addresses in cases where it is judged by the access state detecting means that the second remarked unit of tag addresses is set in the access state; and

data reading operation control means for reading one of the N external word data which is obtained according to the external access request of the hit judging means and is stored in a first remarked unit of M data addresses of the data storing means corresponding to the first remarked unit of M tag addresses in cases where the N external word data are written in the first remarked data entry of the data storing means by the data writing operation control means, and reading a piece of required word data stored in a first remarked unit of M data addresses of the data storing means corresponding to the first remarked unit of M tag addresses in cases where the first hit signal output from the hit judging means is received.

11. A method for controlling a writing operation of either a piece of updated word data relating to a writing request or a piece of external word data relating to an external access, comprising the steps of:

storing pieces of word data in each of a plurality of data entries in a data storing means, N pieces of word data being stored in each of the data entries, each of the word data being stored in M data addresses, and a set of M data addresses for a piece of word data functioning as an administrative unit;

registering a plurality of tag addresses in a plurality of tag entries of a tag means and registering a plurality of entry states respectively determined for a unit of M tag addresses in the tag means, M×

N tag addresses being registered in each of the tag entries, N entry states being determined in each of the tag entries, the tag entries corresponding to the data entries in one-to-one correspondence, the tag addresses corresponding to one of the data addresses in one-to-one correspondence, the entry states being classified into an effective state, an invalid state and an access state, the effective state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is effective, the invalid state set for a unit of M tag addresses indicating that a piece of word data stored in M data addresses corresponding to the unit of M tag addresses is invalid, and the access state for a unit of M tag addresses indicating that an external access for searching for a piece of external word data expected to be stored in M data addresses corresponding to the unit of M tag addresses is under performance;

inputting a first input tag address relating to a reading request to a hit judging means;

judging whether or not a remarked unit of M tag addresses which is represented by the first input tag address and is set in the effective state is registered in the tag means;

requesting an external access to obtain N pieces of external word data expected to be stored in a remarked tag entry of the data storing means corresponding to a first remarked tag entry of the tag means which is designated by the first input tag address in cases where an entry state of the remarked unit of M tag addresses set in the effective state is not registered in the tag means;

preparing the remarked unit of M tag addresses set in the access state and other units of M tag addresses in the tag means to prepare a remarked unit of M data addresses corresponding to the remarked unit of M tag addresses and other units of M data addresses corresponding to the other units of M tag addresses in the data storing means in cases where the remarked unit of M tag addresses set in the effective state is not registered in the tag means;

inputting a second input tag address relating to a writing request to the hit judging means, the remarked unit of M tag addresses being represented by the second input tag address;

changing the state of the remarked unit of M tag addresses set in the access state to the effective state in cases where the external access is finished before the second input tag address relating to the writing request is input;

writing the external data obtained according to the external access in the remarked unit of M data addresses of the data storing means in cases where the external access is finished before the second input tag address relating to the writing request is input;

detecting that the entry state of the remarked unit of M tag addresses is set in the access state in cases where the second input tag address relating to the writing request is input before the external access is finished;

changing the entry state of the remarked unit of M tag addresses set in the access state to the effective state to forbid a writing operation of the external word data obtained according to the external access in the remarked unit of M tag addresses in cases where the remarked unit of M tag addresses set in the access state is detected;

writing a piece of updated word data relating to the writing request in the remarked unit of M data addresses of the data storing means at the same time that the remarked unit of M tag addresses set in the access state is changed to the effective state, the updated word data written in the remarked unit of M data addresses being not replaced with the external word data;

reading out the updated word data stored in the remarked unit of M data addresses according to the reading request after the external access is finished in cases where the second input tag address relating to the writing request is input before the external access is finished; and

reading out the external word data stored in the remarked unit of M data addresses according to the reading request after the external access is finished in cases where the external access is finished before the second input tag address relating to the writing request is input.