Method and apparatus for skipping a snoop phase in sequential accesses by a processor in a shared multiprocessor memory system

• US 5,535,363 A
• Filed: 07/12/1994
• Issued: 07/09/1996
• Est. Priority Date: 07/12/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Prince, Paul E.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US08/273,723
• Time in Patent Office: 728 Days
• Field of Search: 395/473, 395/474, 395/477, 395/478
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

A method and apparatus that allows a snoop phase of a memory transaction to be shortened or skipped is described. During processing of a present memory transaction, the ownership of a system bus during previous memory transactions, as well as the data addresses requested for those transactions, are tracked. If the ownership and requested address of the present transaction match those from the previous transaction, a Next Address signal is provided that allows another transaction to proceed before the snoop phase of the present transaction is completed. In alternate embodiments, the ownership and addresses for multiple transactions are tracked and compared with the ownership and addresses of the present transaction. If a match occurs, the Next Address signal is asserted.

Claims

1. A computer system comprising:

a system bus;

a plurality of microprocessors coupled to said system bus, said plurality of microprocessors including a first microprocessor that generates successive transaction requests including a first transaction request having a first device ID and a first address followed by a second transaction request having a second device ID and a second address;

a first storage element which contains said first device ID and said first address;

a first comparator circuit coupled to said first storage element, said first comparator circuit provides a positive result when said second device ID equals said first device ID and said second address equals said first address; and

a driver circuit coupled to said first comparator circuit, said driver circuit provides a signal indicating to said plurality of microprocessors that said second transaction request may proceed without waiting for a snoop to be performed if said first comparator circuit provides said positive result.

2. The computer system set forth in claim 1 wherein:

said first transaction request and said second transaction request are requested consecutively.

3. The computer system set forth in claim 2 further comprising:

a second storage element which contains a third device ID and a third address from a third transaction request on said system bus, said third transaction request being generated prior to said first and second transaction requests; and

a second comparator circuit coupled to said second storage element, said second comparator circuit provides a positive result when said second address equals said third address if said third device ID equals said first device ID and said second device ID.

4. The computer system set forth in claim 3 wherein:

said driver circuit provides a signal indicating that said second transaction may proceed without waiting for said snoop to be performed if said first comparator circuit or said second comparator circuit provides a positive result.

5. A method for maintaining data coherency in a multiprocessor computer system comprising the steps of:

a) requesting on a system bus a first transaction having a first device ID and a first address;

b) storing said first device ID and said first address;

c) requesting on said system bus a second transaction having a second device ID and a second address;

d) generating a positive result when said second device ID equals said first device ID and said second address equals said first address;

e) indicating that said second transaction may proceed without waiting for a snoop to be performed if step d) provides a positive result.

6. The method set forth in claim 5 further comprising the step of:

storing a third device ID and a third address from a third transaction request made on said system bus, said first transaction request is requested consecutively to said third transaction request.

7. The method set forth in claim 6 wherein step c) further comprises:

comparing said second address with said third address if said third device ID equals said first device ID and said second device ID.

8. The method set forth in claim 7 wherein step d) comprises the step of:

indicating that said second transaction may proceed without waiting for said snoop to be performed if step c) provides said positive result.

9. A computer system comprising:

means for generating on a system bus successive transaction requests including a first transaction request having a first device ID and a first address followed by a second transaction request having a second device ID and a second address;

means for storing said first device ID and said first address;

first means for providing a positive result when said second device ID equals said first device ID and said second address equals said first address; and

means for indicating that said second transaction request may proceed without waiting for a snoop to be performed if said first means for providing provides said positive result.

10. The computer system set forth in claim 9 wherein:

said first transaction request and said second transaction request are generated consecutively.

11. The computer system set forth in claim 10 further comprising:

means for storing a third device ID and a third address from a third transaction request generated on said system bus by said means for generating, said first transaction requested after and consecutive to said third transaction; and

second means for providing said positive result when said second address equals said third address if said third device ID equals said first device ID and said second device ID.

12. The computer system set forth in claim 11 wherein:

said means for indicating indicates that said second transaction may proceed without waiting for said snoop to be performed if either said first means for providing or said second means for providing indicates said positive result.

13. A controller controlling a plurality of microprocessors, the controller comprising:

an interface circuit which receives successive transaction requests and performs a snoop after each transaction request, said transaction requests include a first transaction request having a first device ID and a first address followed by a second transaction request having a second device ID and a second address;

a first storage element coupled to said interface circuit, said first storage element receives and temporarily contains said first device ID and said first address;

a first comparator circuit coupled to said first storage element, said first comparator circuit provides a positive result when said second device ID equals said first device ID and said second address equals said first address; and

a driver circuit coupled to said first comparator circuit, said driver circuit provides a signal which indicates to the plurality of microprocessors that said second transaction request may proceed without waiting for said snoop to be performed if said first comparator circuit provides said positive result.

14. The controller set forth in claim 13 wherein:

said first transaction request and said second transaction request are requested consecutively.

15. The controller set forth in claim 14 further comprising:

a second storage element coupled to said interface circuit, said second storage element receives and temporarily contains a third device ID and a third address from a third transaction request, said third transaction request being received prior to said first and second transaction requests; and

a second comparator circuit coupled to said second storage element, said second comparator circuit provides a positive result when said second address equals said third address if said third device ID equals said first device ID and said second device ID.

16. The controller set forth in claim 15 wherein:

said driver circuit provides a signal to the plurality of microprocessors indicating that said second transaction may proceed without waiting for said snoop to be performed if at least one of said first comparator circuit and said second comparator circuit provides a positive result.

17. A controller controlling a plurality of microprocessors, the controller comprising:

means for receiving successive transaction requests and for performing a snoop after each of said transaction requests, said transaction requests include at least a first transaction request having a first device ID and a first address followed by a second transaction request having a second device ID and a second address;

first means for receiving and temporarily containing said first device ID and said first address;

first comparison means for providing a positive result when said second device ID equals said first device ID and said second address equals said first address; and

means for outputting a signal to the plurality of microprocessors to indicate that said second transaction request may proceed without waiting for said snoop to be performed if said first comparison means provides said positive result.

18. The controller set forth in claim 17 wherein:

said first transaction request and said second transaction request are requested consecutively.

19. The controller set forth in claim 18 further comprising:

second means for receiving and temporarily containing a third device ID and a third address from a third transaction request, said third transaction request being received prior to said first and second transaction requests; and

second comparison means for providing a positive result when said second address equals said third address if said third device ID equals said first device ID and said second device ID.

20. The controller set forth in claim 19 wherein:

said means for outputting provides a signal to the plurality of microprocessors indicating that said second transaction may proceed without waiting for said snoop to be performed if at least one of said first comparison means and said second comparison means provides a positive result.