System for parallel processing that compiles a filed sequence of instructions within an iteration space

• US 5,535,393 A
• Filed: 06/05/1995
• Issued: 07/09/1996
• Est. Priority Date: 09/20/1991
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Mann, William F., Peters, Timothy G., Lee, Linda Q., Kotikian, Jacklin, Rothnie, James B. Jr., Shavit, Tani, Reeve, Christopher L.
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): AMSBURY, WAYNE P
• Application Number:
  US08/461,178
• Time in Patent Office: 400 Days
• Field of Search: 395/600, 395/700
• US Class Current: 717/149
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451

Abstract

An improved parallel processing apparatus and method executes an iterative sequence of instructions by arranging the sequence into subtasks and allocating those subtasks to processors. This division and allocation is conducted in such a manner as to minimize data contention among the processors and to maximize the locality of data to them. The improved apparatus and method have application to a variety of multiprocessor systems, including those which are massively parallel.

Claims

1. In a parallel processor digital data processing apparatus of the type having

a plurality of processing units, each for executing instructions,

memory means coupled to said processing units for storing at least one of data and instructions,

interprocessor communication means coupled to said processing units for transferring information therebetween,

the improvement for processing an iterative sequence of instructions wherein:

A. said memory means includes means for storing a tiled sequence of instructions representing the iterative sequence, and each of said plural processing units includes means for signalling its availability to execute said tiled sequence over a portion of an iteration space associated with said iterative sequence, said portion being referred to as a tile,

B. said apparatus includes next-tile means coupled to said processing units for responding to each of at least selected such signallings by those processing units for generating a signal representing boundaries of a tile over which to execute said tiled sequence, wherein each such tile does not overlap any other tile, wherein each such tile covers a portion less than a whole of said iteration space, and wherein all such tiles together cover said iteration space,

C. each said processing unit including means for responding to a boundary-representative signal generated in response to signalling by that processing unit for executing said tiled sequence over the corresponding tile.

2. In a digital data processing apparatus according to claim 1, the further improvement comprising

A. tile-build means for generating a tile-shape signal indicative of one or more dimensions of said boundary-representative signals, in view of dependency between the corresponding tiles,

B. wherein said tiled sequence includes one or more instructions for write-type access of a datum stored in said memory means,

C. said memory means includes

i) a plurality of memory elements, each for storing at least one of data and instructions, each said memory element being coupled to an associated one of said processing units, and

ii) memory management means coupled with said memory elements for selectively transferring information therebetween, and

D. said next-tile means includes means for generating said boundary-representative signals as a function of said tile-shape signal.

3. In a parallel processor digital data processing apparatus according to claim 2, the further improvement wherein said tile-build means includes means for generating said tile-shape signal indicative of dimensions of said boundary-representative signals that minimize the number of individual datum subject to write-type access during execution of different ones of corresponding tiles.

4. In a parallel processor digital data processing apparatus according to claim 2, the further improvement wherein said tile-build means includes means for generating a tile-shape signal indicative of dimensions of said boundary-representative signals that minimize the number of individual datum subject to write-type access by plural concurrently-executing ones of the processing units.

5. In a parallel processor digital data processing apparatus according to claim 2, wherein

A. first and second tiles include any of

i) an instruction in said first tile that accesses for write-type access a selected datum, and a instruction in said second tile that subsequently accesses for read-type access that same datum,

ii) an instruction in said first tile that accesses for read-type access a selected datum, and an instruction in said second tile that subsequently accesses for write-type access that same datum,

iii) an instruction in said first tile that accesses for write-type access a selected datum, and an instruction in said second tile that subsequently accesses for write-type access that same datum, and

B. said tile-build means includes means for generating a tile-shape signal indicative of dimensions of said boundary-representative signals that minimizes dependence of execution of said second tile upon execution of said first tile with respect to their respective accessing of said selected datum.

6. An apparatus according to claim 2, wherein said tile-build means includes means for generating an affinity signal representative of a tile execution sequence that minimizes a transfer of a data subject to any of read-type and write-type access during execution of successive tiles by different processing units.

7. In a digital data processing apparatus according to claim 2, the further improvement wherein said tile-build means comprises tile-shape means for generating said tile-shape signal as a function of at least one of

i) an affinity signal representing a tile execution sequence that minimizes a transfer of a data subject to any of read-type or write-type access by successive executions of said tiles by different ones of said processing units,

ii) a dependency direction of said tiled sequence,

iii) a processing cost associated with execution of said tiled sequence,

iv) a size of said iteration space,

v) a number of processing units available for execution of said tiled sequence, and

vi) an affinity region signal indicating that the tiled sequence is to be executed within an iteration space defined by a plurality of tile sequences.

8. In a parallel processor digital data processing apparatus according to claim 1, the further improvement wherein

A. said next-tile means includes means for generating successive ones of said boundary-representative signals as a function of at least one of

i) a tile-shape signal indicative of one or more dimensions of said boundary-representative signals,

ii) a tile-strategy signal indicative of at least one of a sequence and manner of assigning tiles to said processing units,

iii) an affinity region signal indicating that the tiled sequence is to be executed within an iteration space defined by a plurality of tile sequences,

B. said apparatus comprises tile-strategy means for generating said tile-strategy signal, and

C. wherein said iteration space is defined by a plurality of indices.

9. In a parallel processor digital data processing apparatus according to claim 8, the further improvement wherein said tile-strategy means includes selectively actuable slice means for

i) generating a tile-shape signal indicative of boundary-representative signals dividing the iteration space by a number of processing units allocated to said execution with respect to one of said indices and spanning the iteration space with respect to the others of those indices, wherein the number of respective tiles is equal to that a number of available processing units, wherein those tiles are substantially equal in size, and

ii) generating a tile-strategy signal indicative of generation of the respective tiles so as to cause one each of them to be executed by a respective one of the available processing units.

10. In a parallel processor digital data processing apparatus according to claim 9, the further improvement wherein said tile-strategy means includes means for actuating said slice means in instances in which

i) data subject to access during execution of any such tile does not depend on that modified during execution of any other such tile, and

ii) no substantial quantity of data subject to any of read-type and write-type access by one such tile is also subject to any of read-type and write-type access by another such tile.

11. In a parallel processor digital data processing apparatus according to claim 9, the further improvement comprising means for actuating said slice means in response to a user-supplied signal.

12. In a parallel processor digital data processing apparatus according to claim 8, the further improvement wherein said tile-strategy means includes selectively actuable modulo means for

i) generating boundary-representative signals to divide the iteration space in fixed-length increments along all of said indices, and

ii) generating a tile-strategy signal indicative of assignment of the respective tiles based on a modulus of a numerical identifier associated with each of the available processing units and a numerical identifier associated with each of the tiles.

13. In a parallel processor digital data processing apparatus according to claim 12, the further improvement wherein said tile-strategy means includes means for actuating said modulo means in instances in which

i) data subject to access during execution of any such tile does not depend on that modified during execution of any other such tile,

ii) no substantial quantity of data subject to any of read-type and write-type access by one such tile is also subject to any of read-type and write-type access by another such tile, and

iii) re-use of data subject to any of read-type or write-type access by a processing unit executing a plurality of tiles is maximized, even in the presence of a change of a size of said iteration space.

14. In a parallel processor digital data processing apparatus according to claim 12, the further improvement comprising means for actuating said modulo means in response to a user-supplied signal.

15. In a parallel processor digital data processing apparatus according to claim 8, the further improvement wherein said tile-strategy means includes selectively actuable wavefront means for

i) generating boundary-representative signals dividing the iteration space along one or more of said indices, wherein data subject to access during execution of at least selected tiles depends on that modified during execution of another tile, and wherein those tiles have a dependency direction,

ii) generating a tile-strategy signal indicative of a sequence of generation of the respective tiles in accord with that dependency direction.

16. In a parallel processor digital data processing apparatus according to claim 15, the further improvement wherein said tile-strategy means includes means for actuating said wavefront means wherein data subject to access during execution of at least one such tile depends on that modified during execution of another such tile.

17. In a parallel processor digital data processing apparatus according to claim 15, the further improvement comprising means for actuating said wavefront means in response to a user-supplied signal.

18. In a parallel processor digital data processing apparatus according to claim 8, the further improvement wherein said tile-strategy means includes selectively actuable modulo/wavefront means for

i) generating boundary-representative signals to divide the iteration space in fixed-length increments along all of said indices, wherein data subject to access during execution of at least a selected tile depends on that modified during execution of one or more other tiles, and wherein said tiles have a dependency direction, and

ii) generating a tile-strategy signal indicative of assignment of the respective tiles based on a modulus of a numerical identifier associated with each of the available processing units and a numerical identifier associated with each of the tiles, and on that dependency direction.

19. In a parallel processor digital data processing apparatus according to claim 18, the further improvement wherein said tile-strategy means includes means for actuating said modulo/wavefront means in instances in which

i) data subject to access during execution of at least one such tile depends on that modified during execution of one or more other such tiles, and

ii) re-use of data subject to any of read-type or write-type access by a processing unit executing a plurality of tiles is maximized, even in the presence of a change of a size of said iterative space.

20. In a parallel processor digital data processing apparatus according to claim 18, the further improvement comprising means for actuating said modulo/wavefront means in response to a user-supplied signal.

21. In a parallel processor digital data processing apparatus according to claim 8, the further improvement wherein said tile-strategy means includes selectively actuable grab means for

i) generating boundary-representative signals to divide the iteration space in fixed-length increments along all of said indices, and wherein data subject to access during execution of any tile does not depend on that modified during execution of any other tile, and

ii) generating a tile-strategy signal indicative of a sequence of generation of the respective tiles, in response to said signalling for availability by said processing units, on a first-come-first-serve basis.

22. In a parallel processor digital data processing apparatus according to claim 21, the further improvement wherein said tile-strategy means includes means for actuating said grab means

i) to facilitate load-balancing among processing units executing said tiles, and in instances when

ii) no substantial quantity of data is subject to any of read-type and write-type access by one such tile is also subject to any of read-type and write-type access by another such tile.

23. In a parallel processor digital data processing apparatus according to claim 21, the further improvement comprising user-responsive means for actuating said wavefront means.

24. In a parallel processor digital data processing apparatus according to claim 1, the further improvement comprising

A. means for providing an affinity region signal representative of one or more iteration sequences that access the same data,

B. affinity region-build means for generating one or more of

i) a signal representative of an iteration space in which one or more tiled sequences within the affinity region are to be executed,

ii) a tile-shape signal representative of one or more dimensions of a boundary-representative signal,

iii) a tile-strategy signal indicative of at least one of a sequence and manner of assigning tiles to said processing units, and

iv) a team signal representative of a set of processing units by which the tiled sequences within the affinity region are to be executed to minimize a transfer of a data subject to any of read-type and write-type access during such execution.

25. In a parallel processor digital data processing apparatus according to claim 24, the further improvement wherein said affinity region-build means includes means for defining said iteration space to encompass one or more of the iteration spaces of the tile sequences in said affinity region.

26. In a parallel processor digital data processing apparatus according to claim 1, the improvement wherein said next-tile means includes means for generating said boundary-representative signals so as to maximize a locality of data subject to access during execution of one or more corresponding tiles, and to minimize contention for access to such data during such execution.

27. In a compiler of the type for translating program signals representative of a program, including an iterative sequence, in source code format into a code sequence of instructions in an object code format suitable for loading for execution by a plurality of parallel digital data processing units,

the improvement comprising

tiling means for responding to said iterative sequence in source code format

for generating a tiled sequence of instructions representative thereof in object code format, and

for further responding to that iterative sequence and to zero, one or more user-specified signals for generating one or more signals representing a framework for generating boundaries for plural tiles over which said tiled sequence is to be executed by said plurality of parallel digital data processing units, each such tile comprising a portion less than a whole of an iteration space associated with said iterative sequence.

28. In a compiler according to claim 27, wherein said compiler includes dependency means for determining a dependency direction of said iterative sequence and for generating a signal representative thereof, the further improvement comprising parallelization means for responding to instructions in said iterative sequence and to said dependency direction-representative signal for generating signals representative of one or more indexes in said iteration space over which to execute said tiled sequence.

29. In a compiler according to claim 28, the further improvement comprising

A. input means for accepting signals representative of a user-specified indexing of said iteration space, and

B. means coupled with said input means and said parallelization means includes means for comparing said user-specified indexing signals with those generated by said parallelization means, and for generating a notification signal in the event of at least selected disagreement thereof.

30. In a compiler according to claim 28, the further improvement comprising optimizing means coupled to said parallelization means for generating one or more signals for use at runtime in optimizing parallel execution of said tiled sequence.

31. In a compiler according to claim 30, the further improvement wherein said optimizing means comprises means for generating an affinity signal representative of a tile execution sequence that minimizes a transfer of data subject to any of read-type or write-type access during execution thereof in plural tiles.

32. In a compiler according to claim 30, the further improvement wherein said optimizing means comprises means for generating an affinity region signal representative of one or more iteration sequences that access the same data.

33. In a compiler according to claim 32, the further improvement comprising

A. input means for accepting signals representative of a user-specified affinity region signal, and

B. means coupled with said input means and said optimizing means includes means for comparing said user-specified affinity region signal with that generated by said optimizing means, and for generating a notification signal in the event of at least selected disagreement thereof.

34. In a compiler according to claim 30, the further improvement wherein said optimizing means comprises means for generating a signal representative of an estimate of a processing cost associated with execution of said tiled sequence.

35. In a compiler according to claim 27, the improvement comprising call-generating means for replacing said iterative sequence in said source code format with an instruction representative of a call to a code-dispatching subroutine.

36. In a compiler according to claim 35, the improvement comprising run-time means for executing said call-representative instruction for initiating execution of said tiled sequence by said processing units.

37. In a method of operating a parallel processor digital data processing apparatus of the type having

a plurality of processing units, each for executing instructions,

memory means coupled to said processing units for storing at least one of data and instructions,

interprocessor communication means coupled to said processing units for transferring information therebetween,

the improvement for processing an iterative sequence of instructions comprising the steps of:

A. storing a tiled sequence of instructions representing the iterative sequence,

B. signalling, for each of said plurality of processing units, its availability to execute said tiled sequence over a portion of an iteration space associated with said iterative sequence, said portion being referred to as a tile,

C. responding to each of at least selected such signallings by those processing units for generating a signal representing boundaries of a tile over which to execute said tiled sequence, wherein each such tile does not overlap any other tile, wherein each such tile covers a portion less than a whole of said iteration space, and wherein all such tiles together cover said iteration space, and

D. each said processor responding to a boundary-representative signal generated in response to signalling by that processing unit for executing said tiled sequence over the corresponding tile.

38. In a method according to claim 37, the further improvement comprising the steps of

A. generating a tile-shape signal indicative of one or more dimensions of said boundary-representative signals, in view of dependency between the corresponding tiles,

B. wherein said tiled sequence includes one or more instructions for write-type access of a datum stored in said memory means,

C. providing a plurality of memory elements, each for storing at least one of data and instructions, each said memory element being coupled to an associated one of said processing units, and selectively transferring information between said memory elements, and

D. generating said boundary-representative signals as a function of said tile-shape signal.

39. In a method according to claim 38, the further improvement comprising generating said tile-shape signal indicative of dimensions of said boundary-representative signals that minimize the number of individual datum subject to write-type access during execution of different ones of corresponding tiles.

40. In a method according to claim 38, the further improvement comprising generating a tile-shape signal indicative of dimensions of said boundary-representative signals that minimize the number of individual datum subject to write-type access by plural concurrently-executing ones of the processing units.

41. In method according to claim 38, wherein

A. first and second tiles include any of

i) an instruction in said first tile that accesses for write-type access a selected datum, and a instruction in said second tile that subsequently accesses for read-type access that same datum,

ii) an instruction in said first tile that accesses for read-type access a selected datum, and an instruction in said second tile that subsequently accesses for write-type access that same datum,

iii) an instruction in said first tile that accesses for write-type access a selected datum, and an instruction in said second tile that subsequently accesses for write-type access that same datum, the further improvement comprising the step of

B. generating a tile-shape signal indicative of dimensions of said boundary-representative signals that minimizes dependence of execution of said second tile upon execution of said first tile with respect to their respective accessing of said selected datum.

42. In a method according to claim 38, the further comprising generating an affinity signal representative of a tile execution sequence that minimizes a transfer of a data subject to any of read-type and write-type access during execution of successive tiles by different processing units.

43. In a method according to claim 38, the further improvement comprising the step of generating said tile-shape signal as a function of at least one of

i) an affinity signal representing a tile execution sequence that minimizes a transfer of a data subject to any of read-type or write-type access by successive executions of said tiles by different ones of said processing units,

ii) a dependency direction of said tiled sequence,

iii) a processing cost associated with execution of said tiled sequence,

iv) a size of said iteration space,

v) a number of processing units available for execution of said tiled sequence, and

vi) an affinity region signal indicating that the tiled sequence is to be executed within an iteration space defined by a plurality of tile sequences.

44. In a method according to claim 37, the further improvement comprising the steps of

A. generating successive ones of said boundary-representative signals as a function of at least one of

i) a tile-shape signal indicative of one or more dimensions of said boundary-representative signals,

ii) a tile-strategy signal indicative of at least one of a sequence and manner of assigning tiles to said processing units,

iii) an affinity region signal indicating that the tiled sequence is to be executed within an iteration space defined by a plurality of tile sequences,

B. generating said tile-strategy signal, and

C. wherein said iteration space is defined by a plurality of indices.

45. In a method according to claim 44, the further improvement comprising selectively actuable slice means for executing the steps of

i) generating a tile-shape signal indicative of boundary-representative signals dividing the iteration space by a number of processing units allocated to said execution with respect to one of said indices and spanning the iteration space with respect to the others of those indices, wherein the number of respective tiles is equal to that a number of available processing units, wherein those tiles are substantially equal in size, and

ii) generating a tile-strategy signal indicative of generation of the respective tiles so as to cause one each of them to be executed by a respective one of the available processing units.

46. In a method according to claim 45, the further improvement comprising the step of actuating said slice means in instances in which

i) data subject to access during execution of any such tile does not depend on that modified during execution of any other such tile, and

ii) no substantial quantity of data subject to any of read-type and write-type access by one such tile is also subject to any of read-type and write-type access by another such tile.

47. In a method according to claim 45, the further improvement comprising means actuating said slice means in response to a user-supplied signal.

48. In a method according to claim 44, the further improvement comprising providing selectively actuable modulo means for executing the steps of

i) generating boundary-representative signals to divide the iteration space in fixed-length increments along all of said indices, and

ii) generating a tile-strategy signal indicative of assignment of the respective tiles based on a modulus of a numerical identifier associated with each of the available processing units and a numerical identifier associated with each of the tiles.

49. In a method according to claim 48, the further improvement comprising the steps of actuating said modulo means in instances in which

i) data subject to access during execution of any such tile does not depend on that modified during execution of any other such tile,

ii) no substantial quantity of data subject to any of read-type and write-type access by one such tile is also subject to any of read-type and write-type access by another such tile, and

iii) re-use of data subject to any of read-type or write-type access by a processing unit executing a plurality of tiles is maximized, even in the presence of a change of a size of said iteration space.

50. In method according to claim 48, the further improvement comprising actuating said modulo means in response to a user-supplied signal.

51. In a method according to claim 44, the further improvement comprising providing selectively actuable wavefront means for executing the steps of

i) generating boundary-representative signals dividing the iteration space along one or more of said indices, wherein data subject to access during execution of at least selected tiles depends on that modified during execution of another tile, and wherein those tiles have a dependency direction,

ii) generating a tile-strategy signal indicative of a sequence of generation of the respective tiles in accord with that dependency direction.

52. In a method according to claim 51, the further improvement wherein said tile-strategy means includes means for actuating said wavefront means wherein data subject to access during execution of at least one such tile depends on that modified during execution of another such tile.

53. In method according to claim 51, the further improvement comprising actuating said wavefront means in response to a user-supplied signal.

54. In a method according to claim 44, the further improvement comprising providing selectively actuable modulo/wavefront means for executing the steps of

i) generating boundary-representative signals to divide the iteration space in fixed-length increments along all of said indices, wherein data subject to access during execution of at least a selected tile depends on that modified during execution of one or more other tiles, and wherein said tiles have a dependency direction, and

ii) generating a tile-strategy signal indicative of assignment of the respective tiles based on a modulus of a numerical identifier associated with each of the available processing units and a numerical identifier associated with each of the tiles, and on that dependency direction.

55. In a method according to claim 54, the further improvement comprising the steps of actuating said modulo/wavefront means in instances in which

i) data subject to access during execution of at least one such tile depends on that modified during execution of one or more other such tiles, and

ii) re-use of data subject to any of read-type or write-type access by a processing unit executing a plurality of tiles is maximized, even in the presence of a change of a size of said iterative space.

56. In a method according to claim 54, the further improvement comprising means for actuating said modulo/wavefront means in response to a user-supplied signal.

57. In a method according to claim 44, the further improvement comprising providing selectively actuable grab means for

i) generating boundary-representative signals to divide the iteration space in fixed-length increments along all of said indices, and wherein data subject to access during execution of any tile does not depend on that modified during execution of any other tile, and

ii) generating a tile-strategy signal indicative of a sequence of generation of the respective tiles, in response to said signalling for availability by said processing units, on a first-come-first-serve basis.

58. In a method according to claim 57, the further improvement wherein said tile-strategy means includes means for actuating said grab means

i) to facilitate load-balancing among processing units executing said tiles, and in instances when

ii) no substantial quantity of data is subject to any of read-type and write-type access by one such tile is also subject to any of read-type and write-type access by another such tile.

59. In a method according to claim 57, the further improvement comprising actuating said wavefront means in response to a user-supplied signal.

60. In a method according to claim 37, the further improvement comprising the steps of

A. providing an affinity region signal representative of one or more iteration sequences that access the same data,

B. generating one or more of

i) a signal representative of an iteration space in which one or more tiled sequences within the affinity region are to be executed,

ii) a tile-shape signal representative of one or more dimensions of a boundary-representative signal,

iii) a tile-strategy signal indicative of at least one of a sequence and manner of assigning tiles to said processing units, and

iv) a team signal representative of a set of processing units by which the tiled sequences within the affinity region are to be executed to minimize a transfer of a data subject to any of read-type and write-type access during such execution.

61. In method according to claim 60, the further improvement wherein said affinity region-build means includes means for defining said iteration space to encompass one or more of the iteration spaces of the tile sequences in said affinity region.

62. In a method according to claim 37, the improvement comprising the step of generating said boundary-representative signals so as to maximize a locality of data subject to access during execution of one or more corresponding tiles, and to minimize concentration for access to such data during such execution.

63. In a method for operating a compiler of the type for translating program signals representative of a program, including an iterative sequence, in source code format into a code sequence of instructions in an object code format suitable for loading for execution by a plurality of parallel digital data processing units,

the improvement comprising the steps of

responding to said iterative sequence in source code format for generating a tiled sequence of instructions representative thereof in object code format, and

further responding to that iterative sequence and to zero, one or more user-specified signals for generating one or more signals representing a framework for generating boundaries for plural tiles over which said tiled sequence is to be executed by said plurality of parallel digital data processing units, each such tile comprising a portion less than a whole of an iteration space associated with said iterative sequence.

64. In a method according to claim 63, wherein said compiler includes dependency means for determining a dependency direction of said iterative sequence and for generating a signal representative thereof, the further improvement comprising responding to instructions in said iterative sequence and to said dependency direction-representative signal for generating signals representative of one or more indexes in said iteration space over which to execute said tiled sequence.

65. In a method according to claim 64, the further improvement comprising the steps of

A. accepting signals representative of a user-specified indexing of said iteration space, and

B. comparing said user-specified indexing signals with those generated by said method, and for generating a notification signal in the event of at least selected disagreement thereof.

66. In a method according to claim 64, the further improvement comprising generating one or more signals for use at runtime in optimizing parallel execution of said tiled sequence.

67. In a method according to claim 66, the further improvement comprising generating an affinity signal representative of a tile execution sequence that minimizes a transfer of data subject to any of read-type or write-type access during execution thereof in plural tiles.

68. In a method according to claim 66, the further improvement wherein said optimizing means comprises means for generating an affinity region signal representative of one or more iteration sequences that access the same data.

69. In a method according to claim 68, the further improvement comprising

A. accepting signals representative of a user-specified affinity region signal, and

B. comparing said user-specified affinity region signal with that generated by said method, and for generating a notification signal in the event of at least selected disagreement thereof.

70. In a method according to claim 66, the further improvement comprising generating a signal representative of an estimate of a processing cost associated with execution of said tiled sequence.

71. In a method according to claim 63, the improvement comprising replacing said iterative sequence in said source code format with an instruction representative of a call to a code-dispatching subroutine.

72. In a method according to claim 71, the improvement comprising executing said call-representative instruction for initiating execution of said tiled sequence by said processing units.