System for (N.cndot.M)-bit correlation using N M-bit correlators

• US 5,535,402 A
• Filed: 04/30/1992
• Issued: 07/09/1996
• Est. Priority Date: 04/30/1992
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Leibowitz, Lawrence M., Mai, Tuan A.
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US07/876,151
• Time in Patent Office: 1,531 Days
• Field of Search: 395/275, 395/325, 395/550, 395/800, 364/728.03, 341/122-124, 341/173, 341/183, 342/189
• US Class Current: 708/422
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 7/02 Comparing digital values G06F7/06, G06F7/22, G06F7/38 take precedence

Abstract

An extended length digital correlator threshold circuit for (N·Mit correlation using N M-bit correlators is disclosed. For the exemplary case where N=2, the digital correlator threshold circuit comprises: a first circuit for storing a preselected code word having first and second digital code portions; a first correlator responsive to the first digital code portion and an input digital data stream passing therethrough for periodically producing a first multibit number representative of the number of bit agreements between the bits in the digital data stream and the bits in the first digital code portion; a second correlator responsive to the second digital code portion and the digital data stream passing therethrough from the first correlator for periodically producing a second multibit number representative of the number of bit agreements between the bits in the digital data stream from the first correlator and the bits in the second digital code portion; and a second circuit responsive to said first and second multibit numbers for generating an output signal when the combined number of bit agreements in both of the first and second multibit numbers is at least equal to a preselected threshold number.

Claims

1. A digital threshold circuit comprising:

means for storing a preselected code word having first and second digital code portions;

first means responsive to said first digital code portion from said storing means and to an input serial digital data stream passing through said first means for periodically producing a first multibit number representative of the number of bit agreements between the bits in the serial digital data stream and the bits in said first digital code portion;

second means responsive to said second digital code portion from said storing means and to the serial digital data stream passing through said second means from said first means for periodically producing a second multibit number representative of the number of bit agreements between the bits in the serial digital data stream from said first means and the bits in said second digital code portion;

means for developing a preselected threshold number; and

means responsive to said first multibit number from said first means, to said second multibit number from said second means and to said preselected threshold number from said developing means for generating an output signal when the number of bit agreements in both of said first and second multibit numbers is at least equal to the preselected threshold number.

2. The digital threshold circuit of claim 1 wherein said developing means includes:

means for determining and applying to said generating means a selection signal indicative of the desired preselected threshold number, said generating means being responsive to said selection signal for selecting only the number of bit agreements in both of said first and second multibit numbers which is at least equal to said desired preselected threshold number.

3. The digital threshold circuit of claim 1 wherein:

each of said first and second means is a digital correlator.

4. The digital threshold circuit of claim 1 wherein:

said generating means is a programmable logic array.

5. The digital threshold circuit of claim 1 wherein:

said generating means is a computer.

6. The digital threshold circuit of claim 1 wherein:

said storing means is a programmable read-only memory.

7. The digital threshold circuit of claim 1 wherein:

said storing means is a computer.

8. The digital threshold circuit of claim 1 wherein:

said storing means is a shift register.

9. The digital threshold circuit of claim 1 wherein:

said storing means is selected from the group consisting of a read-only memory, a computer, and a shift register.

10. The digital threshold circuit of claim 1 wherein:

each of said first and second means is a digital correlator;

said generating means is selected from the group consisting of a programmable logic array and a computer.

11. A computer implemented method for achieving digital correlation with thresholding, said method comprising the computer implemented steps of:

storing a preselected code word having first and second digital code portions;

periodically producing from a first correlator a first multibit number representative of the number of bit agreements between the bits in the first digital code portion and the bits in an input serial digital data stream passing through the first correlator;

periodically producing from a second correlator a second multibit number representative of the number of bit agreements between the bits in the second digital code portion and the bits in the serial digital data stream from the first correlator passing through the second correlator;

developing a preselected threshold number; and

generating an output signal when the number of bit agreements in both of the first and second multibit numbers is at least equal to the preselected threshold number.

12. The method of claim 11 wherein the developing step includes the step of:

selecting the preselected threshold number from a plurality of different preselected threshold numbers.

13. A digital threshold circuit comprising:

means for storing a preselected code word having first and second digital code portions;

a first digital correlator responsive to said first digital code portion from said storing means and to an input serial digital data stream passing through said first digital correlator for periodically producing a first multibit number representative of the number of bit agreements between the bits in the serial digital data stream and the bits in said first digital code portion;

a second digital correlator responsive to said second digital code portion from said storing means and to the serial digital data stream passing through said second digital correlator from said first digital correlator for periodically producing a second multibit number representative of the number of bit agreements between the bits in the serial digital data stream from said first digital correlator and the bits in said second digital code portion;

programmable means responsive to said first multibit number from said first digital correlator and to said second multibit number from said second digital correlator for generating a code detection pulse when the number of bit agreements in both of said first and second multibit numbers is at least equal to a preselected threshold number; and

means for selectively generating and applying the predetermined threshold number to said programmable means.

14. The digital threshold circuit of claim 13 wherein:

said storing means is a computer.

15. The digital threshold circuit of claim 13 wherein:

said storing means is a programmable read-only memory device.

16. The digital threshold circuit of claim 15 wherein:

said storage means is selected from the group consisting of a computer, a read-only memory, a programmable read-only memory, an electrically erasable electronically programmable read-only memory, and a shift register.

17. The digital threshold circuit of claim 13 wherein:

said programmable means is a programmable logic array.

18. The digital threshold circuit of claim 13 wherein:

said programmable means is selected from the group consisting of a programmable logic array, a microprocessor and a computer.

19. The digital threshold circuit of claim 13 wherein:

said means for selectively generating a predetermined threshold value is selected from a group consisting of a switching circuit, a logic array, a microprocessor and a computer.

20. A computer implemented method for generating a code detection pulse for a preselected threshold code comprising the computer implemented steps of:

storing a preselected code word having first and second digital code portions;

periodically producing first and second multibit numbers representative of the number of bit agreements between the bits in an input serial digital data stream and the bits of each of the respective stored first and second digital code portions;

providing a preselected threshold number; and

generating the code detection pulse when the number of bit agreements in both of said first and second multibit numbers is at least equal to the preselected threshold number.