Processor chip for parallel processing system

• US 5,535,408 A
• Filed: 05/02/1994
• Issued: 07/09/1996
• Est. Priority Date: 05/31/1983
• Status: Expired due to Fees

• Current Assignee: TM Patents LP
• Original Assignee: Thinking Machines Corporation (Oracle Corporation)
• Inventors: Hillis, W. Daniel
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/237,981
• Time in Patent Office: 799 Days
• Field of Search: 395/200, 395/325, 395/775, 395/800
• US Class Current: 712/16
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes

Abstract

A monolithic processing chip for a parallel processing system comprises a processor circuit and a memory circuit. The processor circuit processes data received from said associated memory circuit in accordance with processor control signals to generate processed data. The memory circuit includes a plurality of registers for storing data, each register including at least one data storage cell including at least one dynamic memory data bit store for storing a data bit. The memory circuit is responsive to memory control signals and register address signals to transmit stored data from the registers to the processor for processing and to store processed data received from the processor circuit in the register identified by the register address signals.

Claims

1. A parallel computer system comprising:

A. a processor array comprising a plurality of integrated circuit chips each comprising a plurality of processor circuits and a plurality of memory circuits, each processor circuit having an associated memory circuit, said processor circuit for processing data received from its associated memory circuit in accordance with processor control signals to generate processed data, each said memory circuit including a plurality of registers for storing data, each register including at least one data storage cell including at least one dynamic memory data bit store for storing a data bit, said memory circuits being responsive to memory control signals and register address signals to

(i) transmit stored data from correspondingly-addressed registers, as identified by the register address signals, to their associated processors for processing during a read operation, and to store processed data received from their associated processors in correspondingly-addressed registers, as identified by said register address signals during a write operation; and

(ii) perform a refresh operation concurrently with said write operations in connection with registers which are not identified by the register address signals; and

B. a host for generating said processor control signals, said memory control signals and said register address signals for controlling the operations of the processor circuits and the memory circuits of said processor array in parallel.

2. A parallel processing system as defined in claim 1 in which:

A. in each said memory circuit, each register further includes;

i. a register data transfer path; and

ii. a cell read/write control circuit for controlling the transfer of data between selected ones of said data storage cells and said register data transfer path in response to cell address signals received by registers of all of said memory circuits in parallel; and

B. each said memory circuit includes a register selector circuit connected to the register data transfer paths of all of said registers for selectively controlling the transfer of data and processed data between register data transfer paths of selected ones of said registers as identified by said register address signals and said processor circuit.

3. A parallel processing circuit as defined in claim 2 in which, in each memory, each register further includes a data buffer circuit connected to the register'"'"'s respective register data transfer path and the memory circuit'"'"'s register selector circuit, the data buffer of each register:

A. buffering data from its register data transfer path during a read phase; and

B. for selected ones of said registers as identified by the register address signals, buffering processed data generated by the associated processor circuit as received by the data buffer circuit from its respective register selector circuit during a processing phase,

each said data buffer circuit coupling the buffered data onto the respective register data transfer path during a write phase, whereby, for a register in each memory circuit that is a selected one of said registers, processed data is written into said register, and, for a register in each memory circuit that is not a selected one of said registers, data transfer to said data buffer circuit during said read phase is written into said register thereby to refresh the register.

4. A parallel processing system as defined in claim 3 in which, in each memory, each said cell read/write control circuit comprises a plurality of cell transfer circuits each associated with a cell for controlling, in response to the cell address signals, the transfer of data from its associated cell to the respective register data transfer path during the read phase and from the respective register data transfer path to its associated cell for storage therein during the write phase.

5. A parallel processing system as defined in claim 3 in which, in each memory circuit, each said data buffer circuit includes:

A. a data store connected to its respective register selector circuit, said data store receiving and storing data as transferred to said register by said register selector circuit in response to said register address signals;

B. a read gate for coupling data from the register transfer data path to both said data store and said respective register selector circuit in response to a read signal defining said read phase; and

C. a write gate for coupling data from said data store to said respective register transfer data path for storage in a cell in response to a write signal defining said write phase.

6. A parallel processing system as defined in claim 5 in which said data as coupled by the data store of each respect memory has a data value represented by one of a selected number of voltage levels, including a high voltage level and a low voltage level, and in which each register further includes a pre-charge circuit for establishing, in response to a pre-charge signal generated by said host received by all of said registers of all of said memory circuits in parallel, a pre-charge voltage level corresponding to said high voltage level on said register data transfer path in advance of said read phase.

7. A parallel processing system as defined in claim 1 in which each said processor circuit further comprises a global signal generating circuit for generating a global status signal in response to processed data and said processor control signals provided by said host, the host receiving said global status signal and using it in connection with generation of said processor control circuits.

8. A parallel processing system as defined in claim 1 in which each said processor circuit further generates message packets and receives message packets, each message packet including a destination identification identifying a processor circuit to receive the message packet, each said integrated circuit chip further including a global router interface circuit responsive to routing control signals for routing each message packet over interconnection links interconnecting said integrated circuit chips in accordance with the message packet'"'"'s respective destination identification, said host generating said routing control signals and coupling them to the global router interface circuits of all of said integrated circuit chips in parallel.