Secondary data transfer mechanism between coprocessor and memory in multi-processor computer system

• US 5,535,414 A
• Filed: 11/13/1992
• Issued: 07/09/1996
• Est. Priority Date: 11/13/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Burge, Benjamin D.
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US07/975,860
• Time in Patent Office: 1,334 Days
• Field of Search: 395/275, 395/575, 395/425, 395/375, 395/827, 395/847, 395/894, 395/280, 395/154
• US Class Current: 710/7
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A computer system having a CPU, a memory subcircuit, a peripheral subcircuit, a primary SCSI controller, which generates a SCSI bus, a coprocessor, and a secondary SCSI controller, also attached to the SCSI bus. These components are operatively connected in such a way that the coprocessor can access the SCSI bus through the secondary SCSI controller without interfering with the CPU'"'"'s ability either to run a program from the memory subcircuit or to receive data and control input from the peripheral subcircuit.

Claims

1. A computer system comprising:

a system bus having connected thereto at least a central processing unit (CPU), a coprocessor for receiving coprocessing commands from said CPU over said system bus, and at least one subcircuit for providing data to said CPU over said system bus, said system bus including system bus data signals and system bus address signals;

a primary bus controller connecting said system bus to a transfer bus, said transfer bus having a storage device connected thereto, said transfer bus including transfer bus data signals and transfer bus address signals; and

a secondary transfer bus controller for transferring data between said coprocessor and said storage device, independently of said system bus, simultaneously while said CPU is receiving data from said subcircuit over said system bus, said secondary transfer bus controller connected to said storage device by said transfer bus and connected to said coprocessor by a secondary transfer bus, said secondary transfer bus including secondary transfer bus data signals and secondary transfer bus address signals.

2. The computer system of claim 1, wherein said at least one subcircuit comprises a memory subcircuit, said memory subcircuit containing programs which are executed by said CPU and which are transferred to said memory subcircuit from said primary bus controller over said system bus, and to said primary bus controller from said storage device over said transfer bus.

3. The computer system of claim 2, wherein said at least one subcircuit further comprises a peripheral subcircuit providing input data to be read by said CPU over said system bus.

4. The computer system of claim 2, wherein said storage device comprises a direct access storage device.

5. The computer system of claim 4, wherein said direct access storage device comprises a compact disc read only memory (CD ROM) device.

6. The computer system of claim 4, wherein said direct access storage device comprises a fixed disc drive.

7. The computer system of claim 1, wherein said transfer bus conforms to small computer system interface (SCSI) bus standard.

8. The computer system of claim 7, wherein said transfer bus comprises a subset of said SCSI bus standard.

9. The computer system of claim 1, wherein said transfer bus conforms to a general purpose interface bus (GPIB) standard.

10. The computer system of claim 9, wherein said transfer bus comprises a subset of said GPIB standard.

11. The computer system of claim 1, wherein said transfer bus comprises a single wire serial network bus.

12. An auxiliary transfer bus controller mechanism for a computer system comprising (i) a system bus having connected thereto at least a central processing unit (CPU), a coprocessor for receiving coprocessing commands from said CPU over said system bus, and at least one subcircuit for providing data to said CPU over said system bus, said system bus including system bus data signals and system bus address signals;

and (ii) a transfer bus connected to said system bus by a primary transfer bus controller, said transfer bus including transfer bus data signals and transfer bus address signals, said transfer bus having a storage device connected thereto;

said auxiliary transfer bus controller mechanism comprising;

a secondary transfer bus controller for transferring data between said coprocessor and said storage device, independently of said system bus, simultaneously while said CPU is receiving data from said subcircuit over said system bus, said secondary transfer bus controller connected to said storage device by said transfer bus; and

a secondary transfer bus connecting said secondary transfer bus controller to said coprocessor, said secondary transfer bus including secondary transfer bus data signals and secondary transfer bus address signals.

13. The auxiliary transfer bus controller of claim 12, wherein said at least one subcircuit comprises a memory subcircuit, said memory subcircuit containing programs which are executed by said CPU and which are transferred to said memory subcircuit from said primary bus controller over said system bus, and to said primary bus controller from said storage device over said transfer bus.

14. The auxiliary transfer bus controller of claim 12, wherein said transfer bus conforms to small auxiliary transfer bus controller interface (SCSI) bus standard.

15. The auxiliary transfer bus controller of claim 14, wherein said transfer bus comprises a subset of said SCSI bus standard.

16. The auxiliary transfer bus controller of claim 12, wherein said transfer bus conforms to a general purpose interface bus (GPIB) standard.

17. The auxiliary transfer bus controller of claim 16, wherein said transfer bus comprises a subset of said GPIB standard.

18. The auxiliary transfer bus controller of claim 12, wherein said transfer bus comprises a single wire serial network bus.