VLSIC semiconductor memory device with cross-coupled inverters with improved stability to errors
First Claim
1. A semiconductor memory device comprising:
- a set of cross-coupled inverters having first and second inverters, said first inverter comprising a first transistor of a first conductivity type and a second transistor of a second conductivity type, said second inverter comprising a primary transistor of said first conductivity type and a secondary transistor of said second conductivity type;
a first diode having a first forward direction which is directed from drains of said primary and said secondary transistors to a gate of said first transistor;
a second diode having a second forward direction which is directed from drains of said first and said second transistors to a gate of said primary transistor; and
an insulating member, wherein;
each of said first and said primary transistors is a thin-film transistor;
said first transistor is formed on said secondary transistor through said insulating member;
said primary transistor is formed on said second transistor through said insulating member;
said first diode is located in the gate of said first transistor; and
said second diode is located in the gate of said primary transistor.
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Accused Products
Abstract
A static random access memory (SRAM) has a plurality of static memory cells each of which has a set of cross coupled inverters having first and second inverters. The first inverter has first and second transistors. The second inverter has primary and secondary transistors. Each of the first and the primary transistors may be, for example, a P-channel transistor. Each of the second and the secondary transistors may be, for example, an N-channel transistor. The static memory cell further has a first diode having a first forward direction and a second diode having a second forward direction. The first forward direction is directed from drains of the primary and secondary transistors to a gate of the first transistor. The second forward direction is directed from drains of the first and the second transistors to a gate of the primary transistor.
45 Citations
5 Claims
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1. A semiconductor memory device comprising:
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a set of cross-coupled inverters having first and second inverters, said first inverter comprising a first transistor of a first conductivity type and a second transistor of a second conductivity type, said second inverter comprising a primary transistor of said first conductivity type and a secondary transistor of said second conductivity type; a first diode having a first forward direction which is directed from drains of said primary and said secondary transistors to a gate of said first transistor; a second diode having a second forward direction which is directed from drains of said first and said second transistors to a gate of said primary transistor; and an insulating member, wherein; each of said first and said primary transistors is a thin-film transistor; said first transistor is formed on said secondary transistor through said insulating member; said primary transistor is formed on said second transistor through said insulating member; said first diode is located in the gate of said first transistor; and said second diode is located in the gate of said primary transistor. - View Dependent Claims (2, 3, 4, 5)
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Specification