Method for testing an on-off function of semiconductor devices which have an isolated terminal
First Claim
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1. In an apparatus including:
- a plurality of first signal lines;
a plurality of second signal lines crossing said first signal lines; and
a plurality of semiconductor devices, each disposed at each intersection point of one of the plurality of said first signal lines and one of the plurality of said second signal lines, and each semiconductor device having a control terminal connected to a corresponding one of the plurality of said first signal lines to which the semiconductor device is connected, a first main terminal connected to a corresponding one of the plurality of said second signal lines to which the semiconductor device is connected, and a second main terminal which is electrically isolated from the outside by a dielectric material;
a testing method for each of the semiconductor devices comprising the steps of;
(a) applying a voltage which changes with time to said second main terminal through the dielectric material;
(b) applying a control signal which controls conduction and non-conduction of said semiconductor device to said control terminal; and
(c) detecting a displacement current flowing through at least one of said two main terminals and said control terminal.
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Abstract
A testing method is provided for a semiconductor device which includes a control terminal and a pair of main terminals wherein one of the main terminals is isolated from the outside by a dielectric. First, a voltage which changes with time is applied to the isolated main terminal through the dielectric. A control signal which controls conduction and non-conduction of the semiconductor device is the applied to the control terminal. Following this, the test is made by detecting a displacement current flowing through at least one of the two main terminals and the control terminal.
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Citations
20 Claims
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1. In an apparatus including:
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a plurality of first signal lines; a plurality of second signal lines crossing said first signal lines; and
a plurality of semiconductor devices, each disposed at each intersection point of one of the plurality of said first signal lines and one of the plurality of said second signal lines, and each semiconductor device having a control terminal connected to a corresponding one of the plurality of said first signal lines to which the semiconductor device is connected, a first main terminal connected to a corresponding one of the plurality of said second signal lines to which the semiconductor device is connected, and a second main terminal which is electrically isolated from the outside by a dielectric material;
a testing method for each of the semiconductor devices comprising the steps of;(a) applying a voltage which changes with time to said second main terminal through the dielectric material; (b) applying a control signal which controls conduction and non-conduction of said semiconductor device to said control terminal; and (c) detecting a displacement current flowing through at least one of said two main terminals and said control terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for testing whether or not a semiconductor device has an on-off function, wherein said semiconductor has two main terminals and a control terminal, and wherein one of said two main terminals is isolated electrically by a dielectric material from the outside, said method comprising the steps of:
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(a) applying a voltage which changes with time to said one of two main terminals through the dielectric material; (b) applying a control signal which controls conduction and non-conduction of said semiconductor device to said control terminal; and (c) detecting a displacement current flowing through at least one of said two main terminals and said control terminal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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Current AssigneePanasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
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Original AssigneeHitachi, Ltd.
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InventorsSuzuki, Masayoshi, Kawakami, Hideaki, Ohwada, Jun-ichi, Kitazima, Masaaki, Suzuki, Kenkichi
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Primary Examiner(s)Nguyen, Vinh P.
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Application NumberUS06/837,677Time in Patent Office3,781 DaysField of Search324/158.1, 324/73.1, 324/765, 324/768, 324/769, 324/770, 324/671, 324/537, 324/538, 324/662, 324/765, 437/8, 371/15.1, 364/550, 364/551.01US Class Current324/762.01CPC Class CodesG09G 3/006 Electronic inspection or te...
