Shared memory for split-panel LCD display systems

• US 5,537,128 A
• Filed: 08/04/1993
• Issued: 07/16/1996
• Est. Priority Date: 08/04/1993
• Status: Expired due to Term

• Current Assignee: AMBEC 1, S3 Graphics Co., Ltd. (HTC Corporation)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Lin, Dennis Z., Keene, David, Bril, Vlad
• Primary Examiner(s): SARAS, STEVEN J
• Application Number:
  US08/101,770
• Time in Patent Office: 1,077 Days
• Field of Search: 345/87, 345/89, 345/104, 345/185, 345/189, 345/190, 345/196, 345/200, 345/148, 345/98, 345/3.149, 345/103, 345/203, 395/164-166, 395/163, 395/162, 365/221
• US Class Current: 345/89
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3644 with the matrix divided into sections
• CPC Class Codes: G09G 3/3666 with the matrix divided into sections
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

The video memory and the half-frame buffer frame accelerator of a dual scan LCD display are integral in a single memory device. Flat-panel read and write cycles to the frame accelerator designed area inside the memory are optimized in order to minimize memory bandwidth requirements. Extra memory space in the memory device may be used to buffer multiple half-frames of shaded data in such a manner as to save a considerable amount of power in the LCD display graphics system.

Claims

1. A display apparatus to display video information on a dual scan flat panel display device, comprising:

a single memory array having a display memory area and a frame buffer area;

a video controller for causing video information to be displayed on the dual scan flat-panel display device, the video controller reading display data from the display memory area, and storing display data into and retrieving display data from the frame buffer area of the single memory array during display of a frame of the video information, the video controller comprising;

memory cycle arbitration and sequencer for deciding when to retrieve display data from or store display data into said single memory array;

a flat-panel write cycle FIFO with associated full and empty logic;

a flat-panel read cycle FIFO with associated full and empty logic for reading display data from the frame buffer; and

a CRT read cycle FIFO with associated full and empty logic for receiving display data from the display memory area,

wherein the flat panel write cycle FIFO, the flat-panel read cycle FIFO and the CRT read cycle FIFO are all operatively connected to the single memory array;

means responsive to display data read from the display memory area of the single memory array to produce frame-rate modulated, grey-shaded data; and

formatting means for converting frame-rate modulated, grey-shaded data from a data width of the flat-panel display to a data width of the single memory array, the formatting means also converting the display data in the CRT read cycle FIFO from the data width of the single memory array to the data width of the flat-panel display device;

wherein said video controller stores through the flat-panel write cycle FIFO into the frame buffer area the display data converted to the data width of the single memory array, and causes to be displayed on the dual scan flat-panel display device the data converted to the data width of the flat-panel device.

2. A method of operating the apparatus of claim 1, comprising the steps of:

during a blanking interval of the flat-panel display device, filling the flat-panel read cycle FIFO with display data from the frame buffer area of the single memory array; and

at intervals during an active display period, writing multiple stages of data from the flat-panel write cycle FIFO to the frame buffer area of the single memory array and thereafter reading multiple stages of data from the frame buffer area of the single memory array into the flat-panel read cycle FIFO, whereby no delay is incurred during a transition from write cycles to read cycles.

3. A method of displaying video data on a flat-panel display device having a plurality of display panels, comprising the steps of:

producing video data corresponding to a first picture element to be displayed on one of said plurality of display panels;

mapping said video data corresponding to first picture element into a first temporal sequence of display data to be successively displayed at said first picture element to create at said first picture element a visual impression in accordance with said video data;

sending a first one of said display data in said first temporal sequence to said one of said plurality of display panels;

storing a plurality of said display data, occurring after said first one of said data in said temporal sequence, in a buffer memory;

during a same refresh cycle, retrieving from said buffer memory a display data previously stored in said buffer memory and sending said display data to another of said plurality of display panels;

during a next screen refresh cycle, retrieving from said buffer memory and sending to said one display panel a next one of said plurality of display data in said temporal sequence for display at said first picture element;

during said next screen refresh cycle;

retrieving from said buffer memory a display data previously stored in said buffer memory and sending said display data to said one of said plurality of display panels;

producing video data corresponding to a second picture element to be displayed on said another display panel;

performing a mapping of said video data corresponding to said second picture element onto a second temporal sequence of display data to be successively displayed at said second picture element to create at said second picture element a visual impression in accordance with said video data;

sending a first one of said display data in said second temporal sequence to said another of said display panels;

storing a plurality of said display data, occurring after said first one of said display data in said second temporal sequence, in said buffer memory; and

during each of a following screen refresh cycle after said next screen refresh cycle and a next following screen refresh cycle after said following screen refresh cycle;

retrieving a display data previously stored in said buffer memory and sending said display data to said one of said plurality of display panels; and

retrieving a display data previously stored in said buffer memory and sending said display data to said another of said plurality of display panels.

4. A display apparatus to display video information on a dual scan flat panel display device, comprising:

a single memory array having a display memory area and a frame buffer area, the display memory area storing display data corresponding to video information to be displayed;

a video memory controller having a read FIFO, a write FIFO, and a CRT FIFO, the CRT FIFO receiving the display data of a present frame from the display memory area, the write FIFO receiving grey-shaded data corresponding to the present frame and storing the received grey-shaded data into the frame buffer area, the read FIFO receiving the grey-shaded data of a previous frame from the frame buffer area and sending the received grey-shaded data of the previous frame for display on a first half of the dual scan flat panel display device;

a dithering circuit for receiving display data corresponding to the present frame from the CRT FIFO of the video memory controller and generating the grey-shaded data of the present frame; and

a frame rate modulation circuit coupled to the dithering circuit to receive the grey-shaded data of the present frame and to the write FIFO to provide the write FIFO with the grey-shaded data of the present frame, the frame modulation circuit displaying the grey-shaded data of the present frame on the second half of the dual scan flat panel display device.

5. The display apparatus of claim 4 wherein data width of the single memory array is different from data width of the dual scan flat panel device, and wherein the grey shaded data corresponds to the data width of the dual scan flat panel device.

6. The display apparatus of claim 5 further comprising a first converter for converting the grey shaded data to the data width of the single memory array, the first converter sending the converted grey shaded data to the write FIFO.

7. The display apparatus of claim 6 further comprising a second converter for receiving the grey-shaded data from the read FIFO and for converting the received data into the data width of the dual scan flat panel device.

8. A computer system comprising:

a CPU bus;

a dual scan flat panel display device; and

a display apparatus to display video information on the dual scan flat panel display device, comprising;

a single memory array having a display memory area and a frame buffer area, the single memory array receiving display data corresponding to video information to be displayed over the CPU bus and storing display data in the display memory area;

a video memory controller having a read FIFO, a write FIFO, and a CRT FIFO, the CRT FIFO receiving the display data of a present frame from the display memory area, the write FIFO receiving a grey-shaded data corresponding to the present frame and storing the received grey-shaded data into the frame buffer area, the read FIFO receiving the grey-shaded data of a previous frame from the frame buffer area and sending the received grey-shaded data of the previous frame for display on a first half of the dual scan flat panel display device;

a dithering circuit for receiving display data corresponding to the present frame from the CRT FIFO of the video memory controller and generating the grey-shaded data of the present frame; and

a frame rate modulation circuit coupled to the dithering circuit to receive the grey-shaded data of the present frame and coupled to the write FIFO to provide the write FIFO with the grey-shaded data of the present frame, the frame modulation circuit displaying the grey-shaded data of the present frame on the second half of the dual scan flat panel display device.

9. The display apparatus of claim 8 wherein data width of the single memory array is different from data width of the dual scan flat panel device, and wherein the grey shaded data area corresponds to the data width of the dual scan flat panel device.

10. The display apparatus of claim 9 further comprising a first converter for converting the grey shaded data to the data width of the single memory array, the first converter sending the converted grey shaded data to the write FIFO.

11. The display apparatus of claim 10 further comprising a second converter for receiving the grey-shaded data from the read FIFO and for converting the received data into the data width of the dual scan flat panel device.