Apparatus for and method of manufacturing semiconductor wafer

• US 5,537,325 A
• Filed: 04/28/1994
• Issued: 07/16/1996
• Est. Priority Date: 10/29/1991
• Status: Expired due to Fees

• Current Assignee: Komatsu Electronic Metals Co., Ltd. (Sumco Corporation)
• Original Assignee: Komatsu Electronic Metals Co., Ltd. (Sumco Corporation)
• Inventors: Fukushima, Shingo, Iwakiri, Eiji, Takitani, Yukitaka
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): BROWN, THOMAS
• Application Number:
  US08/232,198
• Time in Patent Office: 810 Days
• Field of Search: 364/468, 364/401-403, 364/478, 364/131-136, 364/474.11, 364/474.15, 235/375
• US Class Current: 700/121
• CPC Class Codes: H01L 21/67282 Marking devices
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

When an ingot is sliced into wafers, they are given serial numbers for identification. This makes possible to identify which any wafer being processed is of those sliced from the ingot no matter where the wafer is in a manufacturing process. Each wafer is traced so as to determine the path along which the wafer was transferred during the manufacturing process, and results are stored as wafer information.

Claims

1. An apparatus for manufacturing a plurality of semiconductor wafers, comprising:

identification number applying means for setting an identification number for each of the plurality of semiconductor wafers, said identification number corresponding to a location in a material ingot that a semiconductor wafer was cut from, and for storing the identification numbers in a storage medium as identifier information;

wafer information storing means for tracing as new identifier information a processing path indicative of how the wafer was transferred and how the wafer was processed in each of manufacturing steps on each wafer basis in association with the identifier information in a previous step and for additionally storing the new identifier information as wafer information in the storage medium; and

wafer history management means for performing management over history of each wafer from a lifting step for forming the material ingot throughout entire wafer manufacturing steps on the basis of the stored wafer information.

2. An apparatus for manufacturing semiconductor wafers as set forth in claim 1, characterized in that the new identifier information is expressed in terms of wafer positional coordinates in a jig for accommodation of the wafer in each step.

3. A method for manufacturing semiconductor wafers, comprising:

a step of setting an identification number for each of the semiconductor wafers, said identification number corresponding to a location in a material ingot that a semiconductor wafer was cut from, and of storing the identification numbers in a storage medium as identifier information; and

a wafer information additional storing step of tracing as new identifier information a processing path indicative of how the wafer was transferred and how the wafer was processed in each of manufacturing steps on each wafer basis in association with the identifier information in a previous step and of additionally storing the new identifier information as wafer information in the storage medium,

characterized in that management is carried out over history of each wafer from a lifting step for forming the material ingot throughout entire wafer manufacturing steps on the basis of the stored wafer information.

4. A method for manufacturing semiconductor wafers as set forth in claim 3, characterized in that the new identifier information is expressed in terms of wafer positional coordinates in a jig for accommodation of the wafer in each step.