Complementary architecture for field-programmable gate arrays

• US 5,537,341 A
• Filed: 02/10/1995
• Issued: 07/16/1996
• Est. Priority Date: 02/10/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Jonathan Rose, Vaughn Betz
• Inventors: Rose, Jonathan, Betz, Vaughn
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/387,402
• Time in Patent Office: 522 Days
• Field of Search: 364/579, 364/578, 364/488, 364/489
• US Class Current: 716/104
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

The use of more than one field-programmable gate array design with a given logic capacity produces advantages over the use of a single field-programmable gate array design. The designs of the field-programmable gate arrays in the family are be selected so that each field-programmable gate array design advantageously implements a different type of circuit. This use can select from the family of FPGAs with the same logic capacity such that the circuits can on average be implemented faster and/or in a smaller area.

Claims

1. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, at least two of the designs having the same logic capacity, and the designs having sufficient logic capacity to implement the digital circuit wherein the designs are devised such that each design can advantageously implement a subset of all circuit types;

determining the logic synthesis of the digital circuit into each of the field-programmable gate array designs;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

2. The method of claim 1, wherein the providing step is such that each design is devised so that its respective subset of circuit designs can be implemented with a low delay.

3. The method of claim 1, wherein the providing step is such that each of the designs of the field-programmable gate arrays has the same logic capacity.

4. The method of claim 1, wherein the determining step includes optimizing of the circuit and technology mapping for the logic blocks of the designs.

5. The method of claim 1, wherein the determining step includes the step of choosing the field-programmable gate array with the design that implements the circuit so that the circuit has the lowest delay.

6. The method of claim 1, wherein the determining step includes the step of choosing the field-programmable gate array that succeeds in routing the circuit onto the chip.

7. The method of claim 6, wherein the providing step is such that the field-programmable gate arrays of different designs have the same silicon area.

8. The method of claim 1, wherein the providing step is such that the logic blocks are implemented as look-up tables.

9. The method of claim 1, wherein the providing step is such that the logic blocks of some of the designs have different number of inputs.

10. The method of claim 1, wherein the providing step is such that at least some of the different designs have different patterns of hard-wired connections between logic blocks, said designs also including programmable connections between the logic blocks.

11. The method of claim 10, wherein the providing step is such that at least one of the designs includes multiple groups of more than one logic block, the groups having the same pattern of hard-wired connections between the inputs and outputs of the logic blocks in the group.

12. The method of claim 11, wherein the providing step is such that one design has a group that comprises three logic blocks wherein the pattern of hard-wired connections between the members in the group comprises a hard-wired connection between an output of a first logic block and an input of a second logic block, and a hard-wired connection between an output of a second logic block and an input of a third logic block.

13. The method of claim 11, wherein the providing step is such that one design has a group that comprises three or more logic blocks wherein the pattern of hard-wired connections between the members in the group comprises hard-wired connections between inputs of a first logic block of the group and the outputs of the other logic blocks in the group.

14. The method of claim 1, wherein the providing step is such that at least two of the field-programmable gate arrays have a hierarchical interconnect structure, the first hierarchical interconnect structure design comprising a number of logic blocks connected together with a first level interconnect to form a group and a second number of groups is connected by a second level interconnect, the second hierarchical interconnect structure design comprising a third number of logic blocks connected together with a first level interconnect to form a group and a fourth number of groups is connected by a second level interconnect, wherein the number of logic blocks connected together with a first level interconnect of the first hierarchical interconnect structure design is different than the third number of logic blocks connected together with the first level interconnect of the second hierarchical interconnect structure design.

15. The method of claim 14, wherein the providing step is such that the first hierarchical interconnect structure design has the same total number of logic blocks as the second hierarchical interconnect structure design.

16. The method of claim 14, wherein the providing step is such that the second number of groups connected together with second level interconnect of the first hierarchical interconnect structure design is different than the fourth number of groups connected together with the second level interconnect of the second hierarchical interconnect structure design.

17. The method of claim 1, wherein the providing step is such that at least two of the field-programmable gate arrays are designed in arrays having at least two parallel channels containing sets of routing wires, wherein the distribution of tracks in the channels of the first design is different than the distribution of tracks in the channels of the second design.

18. The method of claim 17, wherein the providing step is such that the at least two of the field-programmable gate arrays are designed in arrays having at least three parallel channels containing sets of routing wires, the channels comprising two outer channels and a middle channel, wherein the middle channel of the first design has more wires than the middle channel of the second design.

19. The method of claim 17, wherein the providing step is such that the first and second design have the same number of total tracks.

20. The method of claim 19, wherein the providing step is such that the first and second design have the same number of logic blocks.

21. The method of claim 1, wherein the providing step is such that at least one of the field-programmable gate arrays is designed with two types of logic blocks having different numbers of inputs.

22. The method of claim 1, wherein the providing step is such that at least two of the field-programmable gate arrays have logic blocks, the first design having a type of logic block with a certain number of inputs not found in the second design.

23. The method of claim 1, wherein the providing step is such that at least two of the field-programmable gate arrays have logic blocks with different numbers of inputs, the two designs having a first type of logic block with one number of inputs and a second type of logic block with a second number of inputs, the first design having a ratio of the number of the first type of logic blocks over the number of second type of logic blocks which is different than this ratio for the second design.

24. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, each design having logic blocks, wherein at least some of the different designs have different patterns of hard-wired connections between logic blocks, said designs also including programmable connections between the logic blocks;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

25. The method of claim 24, wherein the providing step is such that at least one of the designs includes multiple groups of more than one logic blocks, the groups having the same pattern of hard-wired connections between the inputs and outputs of the logic blocks in the group.

26. The method of claim 25, wherein the providing step is such that one design has a group that comprises three logic blocks wherein the pattern of hard-wired connections between the members in the group comprises a hard-wired connection between an output of a first logic block and an input of a second logic block, and a hard-wired connection between an output of second logic block and an input of third logic block.

27. The method of claim 25, wherein the providing step is such that one design has a group that comprises three or more logic blocks wherein the pattern of hard-wired connections between the members in the group comprises hard-wired connections between inputs of a first logic block of the group and the outputs of the other logic blocks in the group.

28. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, each design having logic blocks, wherein at least two of the field-programmable gate arrays are designed in hierarchical interconnect structures, the first hierarchical interconnect structure design comprising a number of logic blocks connected together with a first level interconnect to form a group and a second number of groups is connected by a second level interconnect, the second hierarchical interconnect structure design comprising a third number of logic blocks connected together with a first level interconnect to form a group and a fourth number of groups is connected by a second level interconnect, wherein the number of logic blocks connected together with the first level interconnect of the first hierarchical interconnect structure design is different than the third number of logic blocks connected together with the first level interconnect of the second hierarchical interconnect structure design;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

29. The method of claim 28, wherein the providing step is such that the first hierarchical interconnect structure design has the same total number of logic blocks as the second hierarchical interconnect structure design.

30. The method of claim 28, wherein the providing step is such that the second number of groups connected together with a second level interconnect of the first hierarchical interconnect structure design is different than fourth number of groups connected together with the second level interconnect of the second hierarchical interconnect structure design.

31. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, each design having logic blocks, wherein at least two of the field-programmable gate arrays are designed in arrays having at least two parallel channels containing sets of routing wires, wherein the distribution of wires in the first design is different than the distribution of wires in the second design;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

32. The method of claim 31, wherein the providing step is such that the at least two of the field-programmable gate arrays are designed in arrays having at least three parallel channels containing sets of routing wires, the channels comprising two outer channels and a middle channel, wherein the middle channel of the first design has more wires than the middle channel of the second design.

33. The method of claim 32, wherein the providing step is such that the at least two of the field-programmable gate arrays are designed in arrays having at least three parallel channels containing sets of routing wires, the channels comprising two outer channels and a middle channel, wherein the middle channel of the first design has more wires than one of the outer channels of the first design.

34. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, each design having logic blocks, wherein at least two of the field-programmable gate arrays have logic blocks, the first design having a type of logic blocks having a number of inputs not found in the second design;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

35. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, each design having logic blocks, wherein at least two of the field-programmable gate arrays has logic blocks, the two designs having a first type of logic block with one number of inputs and a second type of logic block with a second number of inputs, the first design having a ratio of the number of the first type of logic blocks over the number of second type of logic blocks than the second design;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

36. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs, at least two of the designs having the same logic capacity, and the designs having sufficient logic capacity to implement the digital circuit wherein the designs are devised such that each design can advantageously implement a subset of all circuit types;

determining the logic synthesis of the digital circuit into each of the field-programmable gate array designs;

determining a preferred design of the field-programmable gate arrays for the digital circuit from the logic synthesis for each of the field-programmable gate array designs; and

implementing the digital circuit on a field-programmable gate array of the preferred design.

37. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs;

determining the logic synthesis of the digital circuit into each of the field-programmable gate array designs;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a single field-programmable gate array of the preferred design,

38. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:

providing a series of field-programmable gate arrays of different designs;

determining the logic synthesis of the digital circuit into each of the field-programmable gate array designs;

determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and

implementing the digital circuit on a field-programmable gate array of the preferred design;

determining the logic synthesis of a second digital circuit into each of the field-programmable gate array designs;

determining the subsequent placement and routing of the different designs to select a different preferred design of the field-programmable gate arrays for the second digital circuit; and

implementing the second digital circuit on a field-programmable gate array of the different preferred design.