×

High-speed processing apparatus and method, signal analyzing system, and measurement apparatus and method

  • US 5,537,344 A
  • Filed: 12/22/1994
  • Issued: 07/16/1996
  • Est. Priority Date: 06/30/1992
  • Status: Expired due to Fees
First Claim
Patent Images

1. A high-speed processing apparatus comprising processing circuit means in a plurality of stages, the processing circuit means of each stage including:

  • a plurality of cascade-connected shift register means for storing input data and successively shifting the input data in response to applied clock pulses;

    a plurality of first storage circuit means for storing function values sampled at a prescribed sampling period with regard to a base function having such a property that a convolution of identical functions becomes the same as the original function;

    a plurality of second storage circuit means for storing function values, sampled at the prescribed sampling period, with regard to a low-pass filter function for converting a frequency of a frequency component possessed by the input data into input data, for the next stage, having a frequency component whose frequency is 1/M of the frequency of the first-mentioned input data, where M represents a positive integer excluding the integer 1;

    a plurality of first multiplying circuit means each for multiplying input data or output data of said shift register means by corresponding function value stored in said first storage circuit means;

    first adding circuit means for adding together output data from these first multiplying circuit means;

    a plurality of second multiplying circuit means each for multiplying input data or output data of said shift register means by corresponding function value stored in said second storage circuit means; and

    second adding circuit means for adding together output data from these second multiplying circuit means;

    multiplication and addition in said processing circuit means of each stage being performed during one period of the clock pulses;

    the shift register means in the processing circuit means of a succeeding stage being provided in a number which is M times that of the shift register means in the processing circuit means of a preceding stage, and data having a sampling period which is M times that of the input data or output data of these shift register means is applied to said first and second multiplying circuit means;

    output data from said second adding circuit means being applied as input data to the processing circuit means of the next stage.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×