High-speed processing apparatus and method, signal analyzing system, and measurement apparatus and method

• US 5,537,344 A
• Filed: 12/22/1994
• Issued: 07/16/1996
• Est. Priority Date: 06/30/1992
• Status: Expired due to Fees

• Current Assignee: KAO Corporation
• Original Assignee: KAO Corporation
• Inventors: Isshiki, Nobuyuki, Uchida, Takanobu, Sannomiya, Kimie, Numata, Toshiharu
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): Ngo, Chuong D.
• Application Number:
  US08/356,250
• Time in Patent Office: 572 Days
• Field of Search: 764/724.01, 764/724.1, 764/724.12, 764/724.16, 764/725, 764/728.01
• US Class Current: 708/400
• CPC Class Codes: G01R 23/16 Spectrum analysis; Fourier analysis
• CPC Class Codes: G06F 17/14 Fourier, Walsh or analogous domain transformations , e.g. Laplace, Hilbert, Karhunen-Loeve, transforms for correlation function computation G06F17/156; spectrum analysers G01R23/16
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G10L 25/27 characterised by the analysis technique

Abstract

A convolution of input data S₀ and a Gabor function G.sub.α,ω is implemented by a processing unit (20) to obtain a wavelet coefficient T_g (2⁰,b) of a 0th stage. The input data S₀ is applied to a low-pass filter (30) and is subjected to Gaussian-type filtering so as to be converted into input data S₁ for a 1st stage. The frequency of the high-frequency components of this input data is halved by this filtering. A convolution of this input data S₁ and a Gabor function G.sub.α /3,2ω/3 is implemented by a processing unit (21) to obtain a wavelet coefficient T_g (2¹,b) of the 1st stage. In the convolution of the 1st stage, the sampling interval is twice that of the 0th stage. Thenceforth, and in similar fashion, the sampling interval in processing operations of subsequent stages is doubled from one stage to the next. As a result, there is no increase in the amount of processing in each stage and a coefficient T_g (2^j,b) can be obtained with identical precision in each stage.

Claims

1. A high-speed processing apparatus comprising processing circuit means in a plurality of stages, the processing circuit means of each stage including:

a plurality of cascade-connected shift register means for storing input data and successively shifting the input data in response to applied clock pulses;

a plurality of first storage circuit means for storing function values sampled at a prescribed sampling period with regard to a base function having such a property that a convolution of identical functions becomes the same as the original function;

a plurality of second storage circuit means for storing function values, sampled at the prescribed sampling period, with regard to a low-pass filter function for converting a frequency of a frequency component possessed by the input data into input data, for the next stage, having a frequency component whose frequency is 1/M of the frequency of the first-mentioned input data, where M represents a positive integer excluding the integer 1;

a plurality of first multiplying circuit means each for multiplying input data or output data of said shift register means by corresponding function value stored in said first storage circuit means;

first adding circuit means for adding together output data from these first multiplying circuit means;

a plurality of second multiplying circuit means each for multiplying input data or output data of said shift register means by corresponding function value stored in said second storage circuit means; and

second adding circuit means for adding together output data from these second multiplying circuit means;

multiplication and addition in said processing circuit means of each stage being performed during one period of the clock pulses;

the shift register means in the processing circuit means of a succeeding stage being provided in a number which is M times that of the shift register means in the processing circuit means of a preceding stage, and data having a sampling period which is M times that of the input data or output data of these shift register means is applied to said first and second multiplying circuit means;

output data from said second adding circuit means being applied as input data to the processing circuit means of the next stage.

2. A high-speed processing apparatus according to claim 1, wherein the processing circuit means of a final stage lacks said second storage circuit means, said second multiplying circuit means and said second adding circuit means.

3. A high-speed processing apparatus comprising:

processing circuit means for performing a repetitive convolution processing operation over a plurality of stages;

memory means for storing, stage by stage, input data applied to said processing circuit means; and

control circuit means for controlling writing of data to and reading of data from said memory means as well as repetition of the processing operation performed by said processing circuit means;

said processing circuit means including;

a plurality of first storage circuit means for storing function values sampled at a prescribed sampling period with regard to a base function having such a property that a convolution of identical functions becomes the same as the original function;

a plurality of second storage circuit means for storing function values sampled at the prescribed sampling period with regard to a low-pass filter function for converting a frequency of a frequency component possessed by the input data into input data, for the next stage, having a frequency component whose frequency is 1/M of the frequency of the first-mentioned input data, where M represents a positive integer excluding the integer 1;

a plurality of first multiplying circuit means which, in the processing operation of each stage, are for multiplying input data of the stage stored in said memory means by corresponding function values stored in said first storage circuit means;

first adding circuit means which, in the processing operation of each stage, are for adding together output data from said first multiplying circuit means;

a plurality of second multiplying circuit means which, in the processing operation of each stage, are for multiplying input data of the stage stored in said memory means by corresponding function values stored in said second storage circuit means; and

second adding circuit means which, in the processing operation of each stage, are for adding together output data from said second multiplying circuit means;

the number of items of input data of each stage stored in said memory means being twice the number of items of input data of the preceding stage;

when input data for a processing operation of a succeeding stage is obtained from said second adding circuit means in the processing operation of each stage, this obtained input data being stored in said memory means as input data of said succeeding stage and the input data of said succeeding stage that has been stored in said memory means being successively shifted;

said control circuit means reading the input data for the processing operation of each stage out of said memory means at a fixed period in such a manner that a readout sampling period of the input data of the succeeding stage becomes M times the readout sampling period of the preceding stage, applying this input data to said processing circuit means and applying data obtained from said second adding circuit means of said processing circuit means to said memory means as the input data of the next stage.

4. A high-speed processing apparatus according to claim 3, wherein whenever repetition of said processing operation over a plurality of stages ends, said control circuit means accepts input data for an initial stage, applies this input data to said processing circuit means, stores the input data in said memory means as input data of the initial stage and neglects input data, for the next stage, obtained in a processing operation of a final stage.

5. A high-speed processing apparatus comprising:

processing circuit means for repeatedly performing a convolution operation;

memory means for storing input data for a processing operation of a succeeding stage to be applied to said processing circuit means; and

control circuit means for controlling writing of data to and reading of data from said memory means as well as repetition of the processing operation performed by said processing circuit means;

said processing circuit means including;

a plurality of first storage circuit means for storing function values sampled at a prescribed sampling period with regard to a base function having such a property that a convolution of identical functions becomes the same as the original function;

a plurality of second storage circuit means for storing function values sampled at the prescribed sampling period with regard to a low-pass filter function for converting a frequency of a frequency component possessed by the input data into input data, for the next stage, having a frequency component whose frequency is 1/M of the frequency of the first-mentioned input data, where M represents a positive integer excluding the integer 1;

a plurality of first multiplying circuit means which, in the processing operation of each stage, are for multiplying input data read out of said memory means by corresponding function values stored in said first storage circuit means;

first adding circuit means which, in the processing operation of each stage, are for adding together output data from said first multiplying circuit means;

a plurality of second multiplying circuit means which, in the processing operation of each stage, are for multiplying input data read out of said memory means by corresponding function values stored in said second storage circuit means; and

second adding circuit means which, in the processing operation of each stage, are for adding together output data from said second multiplying circuit means;

said control means performing an operation of reading input data for a processing operation of an initial stage, in which the number of items of input data is equal to the number of function values stored in said first and second storage means, out of said memory means and applying this input data to said processing circuit means, said operation being performed repeatedly with regard to all input data for the processing operation of the initial stage while the input data to be applied is successively shifted, and successively storing, in said memory means, input data for the next stage obtained from said second adding circuit means for every processing operation in said processing circuit means;

in processing operations of stages following the processing operation of the initial stage, said control circuit means reading, in every stage, input data, the number of items of which is equal to the number of function values, out of said memory means and applying this input data to said processing circuit means, while successively shifting the input data to be read out, at a readout sampling period which is M times the readout sampling period of the input data from said memory means in the processing operation of the preceding stage, and successively storing the input data for the next stage obtained from said second adding circuit means in said memory means for every processing operation in said processing circuit means; and

in a processing operation of a final stage, said control circuit means performing solely an operation of reading the input data out of said memory means and applying this input data to said processing circuit means.

6. A high-speed processing apparatus comprising:

processing circuit means of a plurality of stages for executing a convolution of input data and function data of a base function having such a property that a convolution of identical functions becomes the same as the original function; and

low-pass filtering circuit means of a number of stages one less than that of said processing circuit means for converting a frequency component possessed by the input data of a preceding stage into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1;

the function data in said processing circuit means of each stage being extended over a range M times that of function data in the processing circuit means of a preceding stage;

said processing circuit means and low-pass filtering circuit means of each stage respectively executing convolution and low-pass filtering operations at a sampling period whose period is M times that of the sampling period in the processing circuit means and low-pass filtering circuit means of the preceding stage;

input data for the processing circuit means of an initial stage being applied to the low-pass filtering circuit means of the initial stage and input data obtained from each low-pass filtering circuit means being applied to the processing circuit means of the next stage and the low-pass filtering circuit means of the next stage.

7. A high-speed processing method comprising the steps of:

using processing circuit means of a plurality of stages for executing a convolution of input data and function data of a base function having such a property that a convolution of identical functions becomes the same as the original function, and low-pass filtering circuit means of a number of stages one less than that of said processing circuit means for converting a frequency component possessed by the input data of a preceding stage into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1;

setting function data, which is extended over a range M times that of function data set in the processing circuit means of a preceding stage, in said processing circuit means of each stage;

causing said processing circuit means and low-pass filtering circuit means of each stage to respectively execute convolution and low-pass filtering operations at a sampling period whose period is M times that of the sampling period in the processing circuit means and low-pass filtering circuit means of the preceding stage; and

applying input data for the processing circuit means of an initial stage to the low-pass filtering circuit means of the initial stage, and applying input data obtained from each low-pass filtering circuit means to the processing circuit means of the next stage and the low-pass filtering circuit means of the next stage.

8. A high-speed processing method comprising the steps of:

using processing means, which has been set beforehand to function data of a base function having such a property that a convolution of identical functions becomes the same as the original function, for executing a convolution of input data and this function data, low-pass filtering means for converting a frequency component possessed by the input data into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1, and storage means for storing, stage by stage, the input data to be used by said processing means;

storing input data in said storage means in such a manner that the number of items of data of each stage becomes M times the number of items of input data of the preceding stage, and, when the input data for the initial stage has been applied, and when the input data for the next stage has been obtained from said low-pass sampling means in the processing operation of each stage, storing the items of input data in said storage means as input data of the corresponding stage, and successively shifting the input data of the corresponding stage stored in said storage means;

when the input data for the initial stage has been applied, reading the input data for the initial stage out of said storage means and applying this input data to said processing means and said low-pass filtering means, adopting the data obtained from said processing means as output data of the initial stage, and storing the data obtained from said low-pass filtering means in said storage means as input data for the next stage;

in stages from the next stage onward, reading the input data for the processing operation of each stage out of said storage means and applying this input data to said processing means and said low-pass filtering means at a fixed period in such a manner that the readout sampling period of the input data of the succeeding stage becomes M times the readout sampling period of the preceding stage, adopting the data obtained from said processing means as the output data of each stage and applying the data obtained from said low-pass filtering means to said storage means as input data of the next stage;

Repeating the above-described operation over a prescribed number of stages and disabling said low-pass filtering means in a final stage; and

whenever repetition of the above-described operation over the prescribed number of stages ends, accepting input data for the initial stage and starting the above-described repetitive operation again.

9. A high-speed processing method comprising the steps of:

using processing means, which has been set beforehand to function data of a base function having such a property that a convolution of identical functions becomes the same as the original function, for executing a convolution of input data and this function data, low-pass filtering means for converting a frequency component possessed by the input data into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1, and storage means for storing the input data to be used by said processing means;

performing an operation of reading input data for a processing operation of an initial stage, in which the number of items of input data is equal to the number of function values that have been set in said processing means, out of said storage means and applying this input data to said processing means and said low-pass filtering means, said operation being performed repeatedly with regard to all input data for the processing operation of the initial stage while successively shifting the input data to be applied, adopting the data obtained from said processing means as output data of the initial stage and successively storing, in said storage means, the output data as input data for the next stage obtained from said low-pass filtering means;

in processing operations of stages following the processing operation of the initial stage, reading, in every stage, input data, the number of items of which is equal to the number of function values, out of said storage means and applying this input data to said processing means and said low-pass filtering means, while successively shifting the input data to be read out, at a readout sampling period which is M times the readout sampling period of the input data from said storage means in the processing operation of the preceding stage, adopting the data obtained from said processing means as output data of each stage and successively storing the output data as input data for the next stage obtained from each low-pass filtering means in said storage means; and

performing the above-described operation over a prescribed plurality of stages and, in a processing operation of a final stage, performing solely an operation of reading input data out of said memory means and applying this input data to said processing means.

10. A signal analyzing system comprising:

an input circuit for converting a given physical signal to an electric input signal;

an A/D converting circuit for converting an input signal outputted by said input circuit into digital input data; and

an analytical processing apparatus for analyzing the digital input data outputted by said A/D converting circuit;

said analytical processing apparatus including;

processing means of a plurality of stages for executing a convolution of input data and function data of a base function having such a property that a convolution of identical functions becomes the same as the original function; and

low-pass filtering means of a number of stages one less than that of said processing means for converting a frequency component possessed by the input data of a preceding stage into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1;

the function data in said processing circuit means of each stage being extended over a range M times that of function data in the processing means of a preceding stage;

said processing means and low-pass filtering means of each stage respectively executing convolution and low-pass filtering operations at a sampling period in the processing means and low-pass filtering means of the preceding stage;

input data for the processing means of an initial stage being applied to the low-pass filtering means of the initial stage and input data obtained from each low-pass filtering means being applied to the processing means of the next stage and the low-pass filtering means of the next stage.

11. A signal analyzing system according to claim 10, wherein said processing means and said low-pass filtering means of said plurality of stages are implemented by repeatedly operating a single processing means and a single low-pass filtering means.

12. A signal analyzing system according to claim 10, further comprising a storage device for storing the input data obtained from said A/D converting circuit and data indicative of analytical results obtained from said processing means.

13. A signal analyzing system according to claim 12, further comprising a post-processor for converting the data indicative of the analytical results obtained from said processing means into data suitable for display.

14. A signal analyzing system according to claim 10, further comprising an output unit for outputting, as visible information, the data indicative of the analytical results obtained from said processing means, the data indicative of the analytical results stored in said storage device or post-processed data obtained from the post-processor.

15. A measuring system comprising:

transmitting means for transmitting a physical signal toward an object;

receiving means for receiving the physical signal that returns upon being reflected from the object and converting the physical signal into an electric input signal;

an A/D converting circuit for converting the input signal outputted by said receiving means into digital input data; and

an analytical processing apparatus for analyzing the digital input data outputted by said A/D converting circuit;

said analytical processing apparatus including;

processing means of a plurality of stages for executing a convolution of input data and function data of a base function having such a property that a convolution of identical functions becomes the same as the original function; and

low-pass filtering means of a number of stages one less than that of said processing means for converting a frequency component possessed by the input data of a preceding stage into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1;

the function data in said processing circuit means of each stage being extended over a range M times that of function data in the processing means of a preceding stage;

said processing means and low-pass filtering means of each stage respectively executing convolution and low-pass filtering operations at a sampling period whose period is M times that of the sampling period in the processing means and low-pass filtering means of the preceding stage;

input data for the processing means of an initial stage being applied to the low-pass filtering means of the initial stage and input data obtained from each low-pass filtering means being applied to the processing means of the next stage and the low-pass filtering means of the next stage.

16. A measuring method comprising the steps of:

transmitting a physical signal toward an object;

receiving the physical signal that returns upon being reflected from the object and converting the signal into an electric input signal;

converting the converted electric input signal into digital input data; and

subjecting the converted input data to wavelet analysis;

said wavelet analysis including steps of;

using processing means of a plurality of stages for executing a convolution of input data and function data of a base function having such a property that a convolution of identical functions becomes the same as the original function, and low-pass filtering means of a number of stages one less than that of said processing means for converting a frequency component possessed by the input data of a preceding stage into input data, for the next stage, having a frequency component which is 1/M of the first-mentioned frequency component, where M represents a positive integer excluding the integer 1;

setting function data, which is extended over a range M times that of function data set in the processing means of a preceding stage, in said processing means of each stage;

causing said processing means and low-pass filtering means of each stage to respectively execute convolution and low-pass filtering operations at a sampling period whose period is M times that of the sampling period in the processing means and low-pass filtering means of the preceding stage;

applying input data for the processing means of an initial stage to the low-pass filtering means of the initial stage and applying input data obtained from each low-pass filtering means to the processing means of the next stage and the low-pass filtering means of the next stage; and

obtaining data indicative of results of wavelet analysis from said processing means.