Single chip error processor
First Claim
1. An error processor for providing hardware syndrome generation and analysis, said error processor being disposed on a single integrated circuit chip to detect errors in a block of received data and to generate an error correction vector, said error processor being in communicative relationship with an external communications bus and comprising:
- a) processing hardware means for;
i) receiving data and for generating syndrome bytes corresponding to said received data,ii) detecting errors in said received data and for generating error correction vectors indicative of the relative locations of said errors and of the values thereof, andiii) generating checkbytes as a function of the received data; and
b) interface means operatively connected to said processing hardware means and to said external communications bus for facilitating data transfer therebetween,further comprising dummy vector generating means for generating a predetermined dummy error value in an error correction vector upon occurrence of an uncorrectable error.
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Accused Products
Abstract
An error processor on a single integrated circuit chip to detect and correct errors in a block of received data. The error processor includes processing hardware for receiving data and for generating syndrome bytes corresponding to the received data. It also includes processing hardware for detecting errors in the received data and for generating correction vectors to indicate the relative locations and error values thereof. An interface is connected to the processing hardware for facilitating data transfer to and from a communications bus.
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Citations
29 Claims
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1. An error processor for providing hardware syndrome generation and analysis, said error processor being disposed on a single integrated circuit chip to detect errors in a block of received data and to generate an error correction vector, said error processor being in communicative relationship with an external communications bus and comprising:
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a) processing hardware means for; i) receiving data and for generating syndrome bytes corresponding to said received data, ii) detecting errors in said received data and for generating error correction vectors indicative of the relative locations of said errors and of the values thereof, and iii) generating checkbytes as a function of the received data; and b) interface means operatively connected to said processing hardware means and to said external communications bus for facilitating data transfer therebetween, further comprising dummy vector generating means for generating a predetermined dummy error value in an error correction vector upon occurrence of an uncorrectable error. - View Dependent Claims (2, 3)
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4. An error processor for providing hardware syndrome generation and analysis, said error processor being disposed on a single integrated circuit chip to detect errors in a block of received data and to generate an error correction vector, said error processor being in communicative relationship with an external communications bus and comprising:
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a) processing hardware means for; i) receiving data and for generating syndrome bytes corresponding to said received data, ii) detecting errors in said received data and for generating error correction vectors indicative of the relative locations of said errors and of the values thereof, and iii) generating checkbytes as a function of the received data; and b) interface means operatively connected to said processing hardware means and to said external communications bus for facilitating data transfer therebetween, wherein said interface means further comprises; status indicating means for including in said error correction vectors a status indicator identifying a status of a correction operation, dummy vector generating means for generating a predetermined dummy error value in an error correction vector when said status indicator thereof identifies an uncorrectable error.
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5. An error processor for providing hardware syndrome generation and analysis, Said error processor being disposed on a single integrated circuit chip to detect errors in a block of received data and to generate an error correction vector, said error processor being in communicative relationship with an external communications bus and comprising:
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a) processing hardware means for; i) receiving data and for generating syndrome bytes corresponding to said received data, ii) detecting errors in said received data and for generating error correction vectors indicative of the relative locations of said errors and of the values thereof, and iii) generating checkbytes as a function of the received data; and b) interface means operatively connected to said processing hardware means and to said external communications bus for facilitating data transfer therebetween, wherein said processing hardware means comprises a vector FIFO register for accepting said error correction vectors generated by said processing hardware means. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 23, 24)
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18. An error correcting system, comprising an error processor for providing hardware syndrome generation and analysis, said error processor being disposed on a single integrated circuit chip to detect errors in a block of received data and to generate an error correction vector, said error processor being in communicative relationship with a communications bus and including:
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a) processing hardware means for; i) receiving data and for generating syndrome bytes corresponding to said received data, ii) detecting errors in said received data and for generating error correction vectors indicative of the relative locations of said errors and of the values thereof, and iii) generating checkbytes as a function of the received data; and b) interface means operatively connected to said processing hardware means and to said communications bus for facilitating data transfer therebetween, said communications bus further connected to a control means for controlling communication among a plurality of data sources; said control means correcting errors in data transmitted from one of the data sources to another of the data sources, c) said processing hardware means further comprising queue means for storing said error correction vectors and signal means for outputting a VECTOR BYTE AVAILABLE signal to said control means for informing said control means of availability of one of said error correction vectors thereby eliminating a requirement for polling or interrupts, d) said control means being responsive to said VECTOR BYTE AVAILABLE signal by correcting an error identified by an error correction vector in said queue means. - View Dependent Claims (19, 20, 21, 22)
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25. An error processor for providing hardware syndrome generation and analysis, said error processor being disposed on a single integrated circuit chip to detect errors in a sequence of blocks of received data and to generate an error correction vector, said error processor being in communicative relationship with an external communications bus and comprising:
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a) processing hardware means for; i) receiving data and for generating syndrome bytes corresponding to said received data, ii) detecting errors in said received data and for generating error correction vectors indicative of the relative locations of said errors and of the values thereof, and iii) generating checkbytes as a function of the received data; and b) interface means operatively connected to said processing hardware means and to said external communications bus for facilitating data transfer therebetween, c) said processing hardware means comprising;
means for simultaneously;i) processing data for a first data block to generate a syndrome therefor, ii) processing a syndrome generated for a second data block preceding said first data block to generate an error correction vector for said second data block; and iii) storing an error correction vector generated for a third data block preceding said second data block, and means for generating a VECTOR BYTE AVAILABLE signal to inform an external communications controller of availability of an error correction vector thus eliminating a requirement for polling or interrupts. - View Dependent Claims (26, 27, 28, 29)
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Specification