Transceiver apparatus employing wideband FFT channelizer with output sample timing adjustment and inverse FFT combiner for multichannel communication network

• US 5,537,435 A
• Filed: 04/08/1994
• Issued: 07/16/1996
• Est. Priority Date: 04/08/1994
• Status: Expired due to Term

• Current Assignee: Treble Investments LLC (Intellectual Ventures LLC)
• Original Assignee: AirNet Communications Corporation (Tecore Incorporated)
• Inventors: Williams, Terry, Carney, Ronald
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/224,754
• Time in Patent Office: 830 Days
• Field of Search: 375/229-233, 375/219, 375/259, 375/260, 370/18, 370/29, 370/23, 370/58.1, 370/123, 370/70, 370/97
• US Class Current: 375/219
• CPC Class Codes: H04B 1/0014 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04J 1/05 using digital techniques

Abstract

A physically compact, multichannel wireless communication transceiver architecture employs overlap and add or polyphase signal processing functionality, for wideband signal processing, together with a sample rate. A receiver section receives a plurality of multiple frequency communication channels and outputs digital signals representative of the contents of the plurality of multiple frequency communication channels. The receiver section contains an FFT-based channelizer that processes the digital signals output by a wideband digital receiver and couples respective channel outputs to a first plurality of digital signal processor units, which process (e.g. demodulate) respective ones of the digital channel signals and supply processed ones of the digital channel signals at respective output ports for distribution to an attendant voice/data network. On the transmit side, a transmit section contains a plurality of digital signal processors, respectively associated with respective ones of a plurality of incoming (voice/data) communication signals to be transmitted over respectively different frequency channels. Their processed (modulated, encoded) outputs are supplied to an inverse FFT combiner. The FFT combiner supplies a combined multichannel signal to a wideband transmitter which transmits a multiple frequency communication channel signal. Each of the channelizer and combiner may be implemented using overlap and add or polyphase filtering.

Claims

1. A transceiver apparatus for a wireless communication network containing multiple frequency communication channels for supporting communications among a plurality of geographically distributed first sites, by way of one or more transceiver sites, said transceiver apparatus being installable at a respective one of said one or more transceiver sites and comprising:

a receiver unit which is operative to receive a plurality of signals from a set of said multiple frequency communication channels and output a digital composite receiver signal representative of the signals received from said set of multiple frequency communication channels;

a Fourier transform based channelizer unit which is coupled to receive the digital composite receiver signal from said receiver unit and is operative to output respective digital channel signals representative of the contents of respective ones of the signals received from the plurality of communication channels received by said receiver unit;

a plurality of rate conversion units, respectively associated with said digital channel signals output by said Fourier transform based channelizer unit and being operative to output interpolated digital channel signals representative of respective ones of said digital channel signals in interpolated form with a sample rate timing different from a sample rate timing of the digital channel signals;

a first plurality of signal processor units, respectively associated with said interpolated digital channel signals output by said rate conversion units and being operative to demodulate respective ones of said interpolated digital channel signals and to supply demodulated ones of said digital channel signals at respective output ports thereof;

a second plurality of signal processor units, respectively associated with respective ones of a plurality of incoming communication signals to be transmitted over respectively different communication channels of said network, and being operative to process respective ones of said plurality of incoming communication signals and to supply processed ones of said incoming channel signals at respective output ports thereof;

a Fourier transform-based combiner unit which is coupled to receive said processed ones of said communication signals processed by said second plurality of digital signal processor units and to output a digital combined transmit signal representative of the contents of the incoming communication signals processed by said second plurality of digital signal processor units; and

a transmitter unit which is operative to transmit a multiple frequency communication channel signal in accordance with the digital combined transmit signal output by said Fourier transform-based combiner unit.

2. A transceiver apparatus according to claim 1, wherein said Fourier transform-based channelizer unit includes an overlap and add filter to which the composite signal output by said receiver unit are coupled, and an N-point fast Fourier transform-based processor coupled to the output of said overlap and add filter.

3. A transceiver apparatus according to claim 2, wherein said overlap and add filter contains a plurality of cascaded filter tap stages, each of plural ones of which comprises a plurality of delay memories switchably coupled in series with one another, so as to selectively enable the delay memories of successive filter tap stages to be coupled in series.

4. A transceiver apparatus according to claim 3, wherein said overlap and add filter has a decimation rate M, and wherein said plurality of delay memories comprises a first delay memory having a length of M data samples and a second delay memory having a length of N-M data samples.

5. A transceiver apparatus according to claim 4, wherein said Fourier transform-based channelizer unit is configured to process successive sets of odd and even numbered filtered data sample outputs of said overlap and add filter.

6. A transceiver apparatus according to claim 5, wherein said Fourier transform-based channelizer unit is configured to multiply filtered data sample output of said overlap and add filter by a complex exponential signal, the resultant product value being coupled to said N-point fast Fourier transform-based processor.

7. A transceiver apparatus according to claim 6, wherein said Fourier transform-based channelizer unit includes a numerically controlled oscillator modulator controlled by filtered data sample outputs of said overlap and add filter so as to effectively multiply said filtered data sample outputs by a complex exponential signal.

8. A transceiver apparatus according to claim 4, wherein said each filter tap stage includes a controllable switch, coupled in a signal flow path between plural delay memories of said stage, and being operative to either selectively enable the plural delay memories of said stage to be connected in series with one another, and thereby in a cascaded signal flow path with other tap stages of said filter, or to feed back the contents of one of said plural delay memories to itself.

9. A transceiver apparatus according to claim 8, wherein said each filter tap stage further includes a coefficient memory which stores a plurality of N weighting coefficients, and a multiplier which is operative to multiply respective weighting coefficients stored in said coefficient memory by data sample values from a signal flow path through said delay memories.

10. A transceiver apparatus according to claim 9, wherein said overlap and add filter further includes a summation stage for summing together products output by respective multipliers of said filter tap stages, the output of said summation stage being coupled to said N-point fast-Fourier transform processor.

11. A transceiver apparatus according to claim 2, wherein said Fourier transform-based channelizer unit is configured to process successive sets of odd and even numbered filtered data sample outputs of said overlap and add filter.

12. A transceiver apparatus according to claim 11, wherein said Fourier transform-based channelizer unit is configured to multiply filtered data sample outputs of said overlap and add filter by a complex exponential signal, the resultant product value being coupled to said N-point fast Fourier transform-based processor.

13. A transceiver apparatus according to claim 12, wherein said Fourier transform-based channelizer unit includes a numerically controlled oscillator modulator controlled by filtered data sample outputs of said overlap and add filter so as to effectively multiply said filtered data sample outputs by a complex exponential signal.

14. A transceiver apparatus according to claim 1, wherein said Fourier transform-based combiner unit includes an N-point fast Fourier transform processor coupled to receive communication channel signals processed by said second plurality of digital signal processor units and an overlap and add filter to which the output of said N-point fast Fourier transform processor are coupled.

15. A transceiver apparatus according to claim 14, wherein said overlap and add filter contains a plurality J of cascaded filter tap stages, each of plural ones of which comprises a plurality of delay memories switchably coupled in series with one another, so as to selectively enable the delay memories of successive filter tap stages to be coupled in series.

16. A transceiver apparatus according to claim 15, wherein said overlap and add filter has a decimation rate M, and wherein said plurality of delay memories comprises a first delay memory having a length of M data samples and a second delay memory having a length of N-M data samples.

17. A transceiver apparatus according to claim 16, wherein said Fourier transform-based combiner unit is operative to multiply Fourier processed data samples by a complex exponential signal, the resultant product value being coupled to said overlap and add filter.

18. A transceiver apparatus according to claim 17, wherein said Fourier transform-based combiner unit includes a numerically controlled oscillator, modulator the output of which is controlled by Fourier processed data samples so as to effectively multiply said Fourier processed data samples by a complex exponential signal.

19. A transceiver apparatus according to claim 14, wherein said Fourier transform-based combiner comprises a plurality of block floating point fast Fourier transform engines, the outputs of which are shifted to align the outputs of the engines to a common scale.

20. A transceiver apparatus according to claim 15, wherein said each filter tap stage includes a coefficient memory which stores a plurality of multiply respective weighting coefficients stored in said coefficient memory by Fourier processed data samples, and an adder to which the output of said multiplier and one of said plurality of delay memories is coupled, said adder having an output coupled to a second of said plurality of delay memories of a successive filter tap stage.

21. A transceiver apparatus according to claim 20, wherein said each filter tap stage includes a controllable switch, coupled in a signal flow path between plural delay memories of said stage, and being operative to either selectively enable the plural delay memories of said stage to be connected in series with one another, and thereby in a cascaded signal flow path with other tap stages of said filter, or to feed back the contents of one of said plural delay memories to itself.

22. A transceiver apparatus according to claim 21, wherein said overlap and add filter has a first tap stage containing a coefficient memory which stores a plurality of N weighting coefficients, a multiplier which is operative to multiply respective weighting coefficients stored in said coefficient memory by Fourier processed data samples, a controllable switch having a first input port coupled to receive a sequence of prescribed data values, a second input port coupled to the output of said adder, and an output port coupled to an N-M sample delay memory, said N-M sample delay memory having an output coupled to said adder to be summed with the output of said multiplier, and wherein the output of the multiplier of said first filter tap stage is coupled to a successive filter tap stage of said overlap and add filter, and wherein said controllable switch is operative to either couple said sequence of prescribed data values to said N-M sample memory or to feed back the contents of said delay memory to itself.

23. A transceiver apparatus according to claim 22, wherein the i-th one of said plurality i of filter tap stages has its adder output coupled to provide a combined signal representative of the contents of the communication channel signals processed by said second plurality of digital signal processor units.

24. A transceiver apparatus according to claim 23, wherein said Fourier transform-based combiner unit is configured to process successive sets of odd and even numbered filtered data samples supplied by said second plurality of digital signal processor units.

25. A transceiver apparatus according to claim 1 in which said rate conversion units each additionally comprise a decimating, linear phase low-pass digital filter.

26. A transceiver apparatus according to claim 25 wherein the decimating low-pass digital filter section additionally comprises:

a filter clock generator, for controlling a set of times at which samples of the digital channel signal are advanced through the decimating low-pass filter.

27. A transceiver apparatus according to claim 1 in which said rate conversion units additionally comprise:

a decimating low pass filter structure, which is connected to receive the respective one of the digital channel signals, and connected to output the interpolated digital channel signals, the decimating low pass filter structure providing one of a plurality, L, of possible filter responses.

28. A transceiver apparatus according to claim 1, wherein said Fourier transform-based channelizer unit includes a polyphase filter to which the digital signals output by said multichannel receiver unit are coupled and an N-point fast Fourier transform-based processor coupled to the output of said polyphase filter.

29. A transceiver apparatus according to claim 28, wherein said polyphase filter comprises a finite impulse response filter containing a plurality of filter tap stages, each of which comprises a delay memory, so that the delay memories of successive filter tap stages are coupled in series, each filter tap stage further including a coefficient memory which stores a plurality of N weighting coefficients, and a multiplier which is operative to multiply respective weighting coefficients stored in said coefficient memory by data sample values from a signal flow path through said delay memories, and a summation stage for summing together products output by respective multipliers of said filter tap stages, the output of said summation stage being coupled to said N-point fast-Fourier transform processor.

30. A transceiver apparatus according to claim 29, wherein said Fourier transform-based channelizer unit is configured to process successive sets of odd and even numbered filtered data sample outputs of said polyphase filter.

31. A transceiver apparatus according to claim 30, wherein said Fourier transform-based channelizer unit is configured to multiply filtered data sample outputs of said polyphase filter by a complex exponential signal, the resultant product value being coupled to said N-point fast Fourier transform-based processor.

32. A transceiver apparatus according to claim 31, wherein said Fourier transform-based channelizer unit includes a numerically controlled oscillator modulator controlled by filtered data sample outputs of said polyphase filter so as to effectively multiply said filtered data sample outputs by a complex exponential signal.

33. A transceiver apparatus according to claim 28, wherein said Fourier transform-based channelizer unit is configured to process successive sets of odd and even numbered filtered data sample outputs of said polyphase filter.

34. A transceiver apparatus according to claim 33, wherein said Fourier transform-based channelizer unit is configured to multiply filtered data sample outputs of said polyphase filter by a complex exponential signal, the resultant product value being coupled to said N-point fast Fourier transform-based processor.

35. A transceiver apparatus according to claim 34, wherein said Fourier transform-based channelizer unit includes a numerically controlled oscillator modulator controlled by filtered data sample outputs of said polyphase filter so as to effectively multiply said filtered data sample outputs by a complex exponential signal.

36. A transceiver apparatus according to claim 1, wherein said Fourier transform-based combiner unit includes an N-point fast Fourier transform processor coupled to receive communication channel signals processed by said second plurality of digital signal processor units and a polyphase filter to which the output of said N-point fast Fourier transform processor are coupled.

37. A transceiver apparatus according to claim 36, wherein said polyphase filter comprises a finite impulse response filter containing a plurality of filter tap stages, each of which comprises a delay memory, so that the delay memories of successive filter tap stages are coupled in series, each filter tap stage further including a coefficient memory which stores a plurality of N weighting coefficients, and a multiplier which is operative to multiply respective weighting coefficients stored in said coefficient memory by data sample values from a signal flow path through said delay memories, and a summation stage for summing together products output by respective multipliers of said filter tap stages, the output of said summation stage being coupled to said multichannel transmitter unit.

38. A transceiver apparatus according to claim 1 in which each rate converter provides as the interpolated output signal a signal consisting of interpolated samples of its respective digital channel signal taken at or near positions of expected peak symbol amplitude for that channel.

39. For use with a wireless communication network having multiple frequency communication channels for supporting communications among a plurality of geographically distributed first sites by way of one or more transceiver sites, a method of transmitting and receiving wideband communication signals at a respective one of said one or more transceiver sites and comprising the steps of:

(a) receiving signals from a plurality of said multiple frequency communication channels and generating a plurality of digital signals representative of the contents of said plurality of multiple frequency communication channels;

(b) Fourier transform based channelizer processing said plurality of digital signals generated in step (a) and producing therefrom respective digital channel signals representative of the contents of respective ones of the signals received from the communication channels in step (a);

(c) converting the sample rate of respective ones of said digital channel signals, to provide respective interpolated digital channel signals representative of respective ones of said digital channel signals in interpolated form at a sample rate timing different from a sample rate timing of the digital channel signals;

(d) processing respective ones of said interpolated digital channel signals;

(e) processing respective ones of a plurality of incoming digital communication signals to be transmitted over respectively different frequency channels of said network;

(f) Fourier transform-processing digital communication signals processed in step (d) and producing therefrom a combined signal representative of the contents of the digital communication channel signals processed in step (e); and

(g) transmitting a multiple frequency communication channel signal in accordance with the combined signal produced in step (f).

40. A method according to claim 39, wherein step (b) comprises filtering said plurality of digital signals generated in step (a) by means of an overlap and add filter and processing the resultant filtered signals by an N-point fast Fourier transform-based processor.

41. A method according to claim 40, wherein said overlap and add filter contains a plurality of cascaded filter tap stages, each of plural ones of which comprises a plurality of delay memories switchably coupled in series with one another, and the step (b) further comprises the step of:

selectively enabling the delay memories of successive filter tap stages to be coupled in series.

42. A method according to claim 41, wherein the step (b) further comprises the step of

(iii) selectively enabling said overlap and add filter has a decimation rate M, and wherein said plurality of delay memories, with a first delay memory having a length of M data samples and a second delay memory having a length of N-M data samples.

43. A method according to claim 42, wherein step (b) comprises Fourier transform-processing successive sets of odd and even numbered filtered data sample outputs of said overlap and add filter.

44. A method according to claim 43, wherein the step (b) further comprises the step of:

(v) multiplying filtered data sample outputs of said overlap and add filter by a complex exponential signal.

45. A method according to claim 39, wherein step (f) comprises applying communication channel signals processed in step (e) to an N-point fast Fourier transform processor and filtering the output of said N-point fast Fourier transform processor by an overlap and add filter.

46. A method according to claim 45, wherein said overlap and add filter contains a plurality of cascaded filter tap stages, each of plural ones of which comprises a plurality of delay memories switchably coupled in series with one another, and the step (vii) further comprises:

selectively enabling the delay memories of successive filter tap stages to be coupled in series.

47. A method according to claim 46, wherein said overlap and add filter has a decimation rate M, and wherein the step (viii) further comprises:

selectively enabling said plurality of delay memories to provide a first delay having a length of M data samples and a second delay having a length of N-M data samples.

48. A method according to claim 47, wherein step (f) further includes the step of:

(ix) multiplying Fourier transform-processed digital communication signals by a complex exponential signal, and

(x) applying the resultant product signal to said overlap and add filter.

49. A method according to claim 46, wherein said each filter tap stage includes a coefficient memory which stores a plurality of weighting coefficients, and step (b) further comprises:

(xi) multiplying respective weighting coefficients stored in said coefficient memory by Fourier processed data samples; and

(xii) adding the output of said multiplying step (xi) and the output of one of said plurality of delay memories, said addition step output being coupled to a second one of said plurality of delay memories of a successive filter tap stage.

50. A method according to claim 49, wherein said each filter tap stage includes a controllable switch, coupled in a signal flow path between plural delay memories of said stage, and step (b) further comprises:

selectively enabling the plural delay memories of said stage to be connected in series with one another, and thereby in a cascaded signal flow path with other tap stages of said filter, to feed back the contents of one of said plural delay memories to itself.

51. A method according to claim 50, wherein said overlap and add filter has a first tap stage containing a coefficient memory which stores a plurality of N weighting coefficients, and step (b) further comprises:

(xiii) multiplying respective weighting coefficients stored in said coefficient memory by Fourier processed data samples; and

(xiv) controllably switching a first input port coupled to receive a sequence of prescribed data values, and a second input port coupled to the output of said addition step (xii), and an output port coupled to an N-M sample delay memory, said N-M sample delay memory having an output coupled to said adder to be summed with the output of said multiplying step (xiii);

(xv) coupling the output of the multiplier of said first filter tap stage to a successive filter tap stage of said overlap and add filter; and

(xvi) operating said controllable switching step to either couple said sequence of prescribed data values to said N-M sample memory or to feed back the contents of said delay memory to itself.

52. A method according to claim 51, additionally comprising the step of coupling an adder to the output of the Jth one of said plurality i of filter tap stages to provide a combined signal to be transmitted in step (g).

53. A method according to claim 39, wherein in steps (b) and (f) the Fourier transform processing is executed with a plurality of block floating point fast Fourier transform engines, the outputs of which are shifted to align the outputs of the engines to a common scale.

54. A method according to claim 39, wherein step (b) comprises filtering said plurality of digital signals generated in step (a) by means of a polyphase filter and processing the resultant filtered signals by an N-point fast Fourier transform-based processor.

55. A method according to claim 54, wherein said polyphase filter comprises a finite impulse response filter containing a plurality of filter tap stages, each of which comprises a delay memory, so that the delay memories of successive filter tap stages are coupled in series, each filter tap stage further including a coefficient memory which stores a plurality of N weighting coefficients, and the step (b) further comprises:

multiplying respective weighting coefficients stored in said coefficient memory by data sample values from a signal flow path through said delay memories;

(xvii) summing together products output by respective multipliers of said filter tap stages; and

(xviii) coupling the output of said summation stage to said N-point fast-Fourier transform processor.

56. A method according to claim 55, wherein step (b) comprises Fourier transform-processing successive sets of odd and even numbered filtered data sample outputs of said polyphase filter.

57. A method according to claim 56, wherein step (b) further comprises the step of:

(xix) multiplying filtered data sample outputs of said polyphase filter by a complex exponential signal; and

(xx) coupling the resultant product value to said N-point fast Fourier transform-based processor.

58. A method according to claim 39, wherein step (f) comprises applying said digital communication channel signals to an N-point fast Fourier transform processor and filtering the output of said N-point fast Fourier transform processor by a polyphase filter.

59. A transceiver apparatus for a wireless communication network containing multiple frequency communication channels for supporting communications, among a plurality of geographically distributed first sites, by way of one or more transceiver sites, said transceiver apparatus being installable at a respective one of said one or more transceiver sites and comprising:

a receiver unit which is operative to receive a plurality of said multiple frequency communication channels and output a digital signal representative of the contents of said plurality of multiple frequency communication channels;

a Fourier transform based channelizer unit which is coupled to receive a digital signal from said receiver unit and is operative to output respective digital channel signals representative of the contents of respective ones of the communication channels received by said receiver unit;

a plurality of rate conversion units, respectively associated with the digital channel signals output by said channelizer unit and being operative to output interpolated digital channel signals representative of respective ones of said digital channel signals in interpolated form, at least one of said rate conversion units including a decimating low pass filter structure, which is connected to receive the respective one of the digital channel signals, and connected to output the interpolated digital channel signals, the decimating low pass filter structure providing one of a plurality, L, of possible filter responses, and in which said decimating low pass filter structure additionally comprises a filter response selection unit, the filter response selection unit connected to the decimating low pass filter structure, to provide a filter selection signal to the decimating low pass filter structure to determine which of the L filter responses is selected as an active filter response at a given time;

a first plurality of signal processor units, respectively associated with the interpolated digital channel signals output by said rate conversion units and being operative to demodulate respective ones of said interpolated digital channel signals and to supply demodulated ones of said digital channel signals at respective output ports thereof;

a second plurality of signal processor units, respectively associated with respective ones of a plurality of incoming communication signals to be transmitted over respectively different frequency channels of said network, and being operative to process respective ones of said plurality of incoming communication signals and to supply processed ones of said communication channel signals at respective output ports thereof;

a Fourier transform,based combiner unit which is coupled to receive communication channel signals processed by said second plurality of digital signal processor units and to output a combined signal representative of the contents of the communication channel signals processed by said second plurality of digital signal processor units; and

a transmitter unit which is operative to transmit a multiple frequency communication channel signal in accordance with the combined signal output by said Fourier transform-based combiner unit.

60. A transceiver apparatus according to claim 59 in which the digital channel signals comprise a preamble portion and a data portion, and wherein the filter response selection unit determines which of the L possible filter responses to select by determining a sampling phase differential during the preamble portion of its respective digital channel signal.

61. A transceiver apparatus according to claim 59 in which the digital channel signals comprise a preamble portion and a data portion, and wherein the filter response selection unit determines which one of the L possible filter responses to select by determining which one of the L possible filter responses provides an optimum response to the preamble portion of the digital channel signal.

62. A transceiver apparatus according to claim 59 in which the digital channel signals comprise a preamble portion and a data portion, and wherein the filter response selection unit additionally comprises:

a plurality, M, of filter sections, each of the M filter sections being one of the L possible filter responses, each filter section providing an intermediate interpolated digital signal.

63. A transceiver apparatus according to claim 59 in which the digital channel signals comprise a preamble portion and a data portion, and wherein the filter response selection unit additionally comprises:

a plurality, M, of filter sections, each of the M filter sections being one of the L possible filter responses, each filter section providing an intermediate interpolated digital signal;

a plurality, M, of correlation units arranged to receive the respective ones of the M intermediate interpolated digital signals and an expected preamble digital signal, and operative to correlate the M filter responses with the expected preamble digital signal, and to provide M correlator output signals;

a comparator, for receiving the M correlator output signals and determining an index, x, of the one of the correlator output signals indicating the greatest correlation between the respective one of the M intermediate interpolated digital signals and the expected preamble digital signal; and

whereby the desired one of the L filter sections is selected by the filter selection unit depending upon the index, x, determined by the comparator.

64. A transceiver apparatus according to claim 63 wherein each of the L filter sections additionally comprises:

a filter clock generator, for controlling a set of times at which samples of the digital channel signal are advanced through the decimating low-pass filter.

65. A transceiver apparatus according to claim 64 wherein the filter clock generator comprises:

a digital channel signal sample index counter, connected to count the samples of the input digital channel signal, and to provide a sample index value;

a multiplier, for multiplying the sample index value by a sample rate adjustment factor, the sample rate adjustment factor depending upon a ratio of the rate of the samples of the input digital channel signal to the rate of the samples of the respective one of the intermediate interpolated digital signals.

66. A transceiver apparatus according to claim 63 wherein only the selected filter having index x is operational during the data portion of the digital channel signal.

67. A transceiver apparatus according to claim 63 additionally comprising

a tracking unit, connected to receive the index value x of the currently selected one of the L filter sections, and also connected to receive at least the intermediate interpolated digital signal from the currently selected filter section, and operating to compare the response of the selected filter section against at least the response of at least one of the other L filter sections, to provide an index value adjustment amount if the said other filter section provides samples closer to the desired position of the samples nearest the symbols in the digital channel signal;

and

an index value adjuster, connected receive the index value, x, and the index value adjustment amount, and arranged to periodically adjust the index value by the adjustment amount.