Neural network elements

• US 5,537,512 A
• Filed: 02/07/1995
• Issued: 07/16/1996
• Est. Priority Date: 05/26/1993
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Mei, Eden Y. C., Hsia, Yukun
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Hafiz, Tariq R.
• Application Number:
  US08/385,236
• Time in Patent Office: 525 Days
• Field of Search: 395/20, 395/23-25, 395/27, 307/201, 307/301, 365/185, 257/4, 382/155-159
• US Class Current: 706/39
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

An analog neural network element includes one or more EEPROMs as analog, reprogrammable synapses applying weighted inputs to positive and negative term outputs which are combined in a comparator. In one embodiment a pair of EEPROMs is used in each synaptic connection to separately drive the positive and negative term outputs. In another embodiment, a single EEPROM is used as a programmable current source to control the operation of a differential amplifier driving the positive and negative term outputs. In a still further embodiment, an MNOS memory transistor replaces the EEPROM or EEPROMs. These memory elements have limited retention or endurance which is used to simulate forgetfulness to emulate human brain function. Multiple elements are combinable on a single chip to form neural net building blocks which are then combinable to form massively parallel neural nets.

Claims

1. A neural network element, comprising:

two analog memory elements each characterized by being programmable and non-volatile and each having gate, source, and drain electrodes, each said analog memory element being configured as a synaptic connection;

an analog operating input having either a positive or a negative value connected to said drain electrodes of said analog memory elements;

a first analog programming input connected to said gate electrode of said first analog memory element;

a second analog programming input connected to said gate electrode of said second analog memory element;

an analog positive term output controlled by said source electrode of said first analog memory element;

an analog negative term output controlled by said source electrode of said second analog memory element, and

output means for combining said positive and negative term outputs, comprising;

a positive term buffer amplifier connected to said single analog positive term output, said positive term buffer amplifier outputting a positive buffer output,

a negative term buffer amplifier connected to said single analog negative term output, said negative term buffer amplifier outputting a negative buffer output, and

a comparator connected to said positive and negative term buffer amplifiers and receiving said positive and negative buffer outputs as positive and negative inputs, respectively, said comparator outputting a comparator output.

2. A neural network element, comprising:

two analog memory elements each characterized by being programmable and non-volatile and each having gate, source, and drain electrodes, each said analog memory element being configured as a synaptic connection;

an analog operating input having either a positive or a negative value connected to said drain electrodes of said analog memory elements;

a first analog programming input connected to said gate electrode of said first analog memory element;

a second analog programming input connected to said gate electrode of said second analog memory element;

an analog positive term output controlled by said source electrode of said first analog memory element;

an analog negative term output controlled by said source electrode of said second analog memory element, and

output means for combining said positive and negative term outputs, comprising;

a positive term buffer amplifier connected to said single analog positive term output, said positive term buffer amplifier outputting a positive buffer output,

a negative term buffer amplifier connected to said single analog negative term output, said negative term buffer amplifier outputting a negative buffer output,

a comparator connected to said positive and negative term buffer amplifiers and receiving said positive and negative buffer outputs as positive and negative inputs, respectively, said comparator outputting a comparator output, and,

a threshold detector connected to said comparator and receiving said comparator output as a detector input, said threshold detector outputting said single analog neural network element output.