Fully pipelined and highly concurrent memory controller

• US 5,537,555 A
• Filed: 03/22/1993
• Issued: 07/16/1996
• Est. Priority Date: 03/22/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Collins, Michael J., Landry, John A., Bonella, Randy M., Santeler, Paul A., Thome, Gary W.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Travis, John
• Application Number:
  US08/034,290
• Time in Patent Office: 1,212 Days
• Field of Search: 395/325, 395/280, 395/285, 395/308, 395/309, 395/310, 395/311
• US Class Current: 710/310
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure

Abstract

A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Claims

1. A computer system comprising:

a processor having address outputs and data and control terminals and executing operations cycles wherein signals are provided on said address outputs and said control terminals indicative of the operation being performed, said control terminals including an output for indicating operation cycle start and an input for receiving an operation cycle completion indication;

a processor bus having address, data and control portions for transmitting address, data and control signals, said processor bus connected to said processor for transmitting signals to and from said processor;

a host bus having address, data and control portions for transmitting address, data and control signals;

a device having address inputs and control and data terminals, said device connected to said host bus for receiving addresses and transmitting and receiving control and data signals over said host bus, said control terminals including an input for receiving an operation cycle start indication and an output for providing an operation cycle completion indication;

a plurality of memory devices having address and control inputs and data terminals;

a memory bus having address, control and data portions and connected to said plurality of memory devices for transferring address and control signals to said plurality of memory devices and data signals to and from said plurality of memory devices;

a data buffer connected to said processor, host and memory data bus portions for transferring data between said buses, said data buffer having control inputs for receiving signals controlling transfers between said buses;

means connected to said processor and host address bus portions for transferring addresses between said buses;

memory address means connected to said processor address bus portion for providing addresses from said processor bus to said memory bus, said memory address means having control inputs for receiving signals controlling said address provision;

means connected to said processor bus for determining whether an operation cycle on said processor bus is directed to said plurality of memory devices or said host bus device; and

a memory controller connected to said processor, host and memory control bus portions, to said data buffer, to said means for transferring addresses between said processor and host buses, to said operation cycle direction determination means and to said memory address means for controlling operation of said data buffer, said means for transferring addresses between said processor and host buses, said memory address means and said plurality of memory devices based on the direction as determined by said operation cycle direction determination means and as sequenced by the operation cycle, wherein said memory controller includes;

a processor control interface portion, said processor control interface portion receiving operation cycle start indications from said processor, providing operation cycle complete indications to said processor, providing control signals to said data buffer for receiving data from said processor data bus and providing data to said processor bus, providing a control signal indicative of receipt of an operation cycle directed to said plurality of memory devices, providing a control signal indicative of receipt of an operation cycle directed to said host bus;

having an input for receiving a signal indicative of completion of said operation cycle to said plurality of memory devices and having an input for receiving a signal indicative of completion of said operation cycle to said host bus;

a host bus control interface portion, said host bus control interface portion receiving said control signal indicative of receipt of an operation cycle directed to said host bus from said processor control interface portion, providing operation cycle start indications to said host bus, receiving operation cycle complete indications from said host bus, providing control signals to said data buffer for receiving data from said host bus and providing data to said host bus and providing a signal to said processor control interface portion indicative of completion of said operation cycle to said host bus; and

a memory control interface portion, said memory control interface portion receiving said control signal indicative of receipt of an operation cycle directed to said plurality of memory devices from said processor control interface portion, providing control signals to said plurality of memory devices, providing control signals to said memory address means to provide an address and control signals to said plurality of memory devices, providing control signals to said data buffer for receiving data from said memory data bus and providing data to said memory data bus and providing a signal to said processor control interface portion indicative of completion of said operation cycle to said plurality of memory devices.

2. The computer system of claim 1, wherein said processor control terminals include an input for receiving a control signal indicating capability to receive the address of the next operation cycle, wherein said processor may then provide the address of the next operation cycle before a pending operation is complete, resulting in pipelining, and

wherein said processor interface control portion has an output for providing a control signal indicating capability to receive the next address and wherein said next address control signal is provided when said memory controller is capable of receiving said next address before a pending operation cycle is complete.

3. The computer system of claim 2, wherein said data buffer includes latches for receiving data from said processor bus for provision of said data to said plurality of memory devices and latches for receiving data from said processor bus for provision of said data to said host bus, and

wherein said processor control interface portion controls said data buffer to latch data from said processor bus to the proper of said latches based on the direction of said operation cycle and provides said operation cycle complete indication to said processor bus when said data is latched and before completion of the cycle to said plurality of memory devices or said host bus as appropriate.

4. The computer system of claim 3, wherein said processor performs burst operation cycles wherein an address is provided and a plurality of sequential data elements are provided, said burst operation cycle utilizing a single operation cycle indication and receiving a plurality of operation cycle complete indications, one for each data element, and

wherein said processor control interface provides a operation cycle completion indication for each data element.

5. The computer system of claim 4, wherein said data buffer latches for provision of data to said plurality of memory devices include a plurality of latches sufficient for receiving all the data elements in a burst operation cycle, and

wherein said processor control interface portion controls said latches in said data buffer to latch all of the data elements in a burst operation cycle.

6. The computer system of claim 3, wherein said processor provides an operation write cycle directed to one of said host bus or said plurality of memory devices followed by an operation cycle directed to the other of said plurality of memory devices or host bus, and

wherein said processor control interface portion provides said control signals to said data buffer and said processor to cause data to be latched in said data buffer, an operation cycle receipt signal is provided to the appropriate of said host bus control interface portion or said memory control interface portion and an operation cycle completion indication is provided to said processor for the first of said cycles and said processor control interface portion receives the operation cycle start indication for the second operation cycle and provides an operation cycle receipt signal to the other of said host bus control interface portion or said memory control interface portion, whereby two operation cycles are concurrently being processed by said memory controller.

7. The computer system of claim 6, wherein said device connected to said host bus comprises:

an input/output bus having address, control and data portions for transmitting address, data and control signals;

a input/output device having address inputs and data and control terminals, said input/output device connected to said input/output bus for receiving addresses and transmitting and receiving control and data signals over said input/output bus;

a data buffer connected between said host and said input/output bus data portions for transferring data between said buses, said data buffer having control inputs for receiving signals controlling transfers between said buses and having latches for receiving data from said host bus for provision to said input/output bus;

means connected to said input/output and host address bus portions for transferring addresses between said buses;

a bus controller connected to said host and input/output bus control portions, to said input/output data buffer and said means for transferring addresses between said input/output and host buses for controlling operation of said input/output data buffer and said means for transferring addresses between said input/output and host buses as sequenced by the operation cycle and performing operation cycles on said input/output bus, said bus controller including an input for receiving an operation cycle start indication on said host bus and an output for providing an operation cycle completion indication on said host bus,

wherein said processor provides an operation directed to said input/output device on said input/output bus prior to providing said operation cycle directed to said host bus, and

wherein said bus controller provides said control signals to said input/output data buffer to cause said input/output data buffer to latch data and provides said operation cycle completion indication to said host bus before completion of the operation cycle on the input/output bus, whereby three operation cycles are concurrently being processed by the computer system.

8. The computer system of claim 7, wherein said operation to the second of said host bus or said plurality of memory devices is a write cycle,

wherein said processor provides an operation cycle following said second operation cycle;

and

wherein said processor control interface portion provides said control signals to said data buffer to cause data for said cycle to be latched in said data buffer, an operation cycle completion indication is provided to said processor for said cycle and said processor control interface portion receives the operation cycle start indication for the operation cycle following said second operation cycle, whereby four operation cycles are concurrently being processed by the computer system, three of them being concurrently processed by said memory controller.

9. The computer system of claim 1, wherein said device connected to said host bus comprises:

an input/output bus having address, control and data portions for transmitting address, data and control signals;

a input/output device having address inputs and data and control terminals, said input/output device connected to said input/output bus for receiving addresses and transmitting and receiving control and data signals over said input/output bus;

a data buffer connected between said host and said input/output bus data portions for transferring data between said buses, said data buffer having control inputs for receiving signals controlling transfers between said buses;

means connected to said input/output and host address bus portions for transferring addresses between said buses;

a bus controller connected to said host and input/output bus control portions, to said input/output data buffer and said means for transferring addresses between said input/output and host buses for controlling operation of said input/output data buffer and said means for transferring addresses between said input/output and host buses as sequenced by the operation cycle and performing operation cycles on said input/output bus, said bus controller including an input for receiving an operation cycle start indication on said host bus and an output for providing an operation cycle completion indication on said host bus; and

a bus master having address outputs and control and data terminals connected to said input/output bus for controlling operation cycles on said input/output bus, wherein said bus master directs operations to said plurality of memory devices,

wherein said bus controller detects said bus master operation cycle directed to said plurality of memory devices and controls said input/output data buffer to transfer data between said input/output and host data bus portions and controls said means connected to said input/output and host address bus portions to transfer addresses between said input/output and host buses,

wherein said memory controller controls said means connected to said processor and host address bus portions for transferring addresses between said processor and host buses to transfer addresses between said processor and host buses when said memory controller detects said bus master cycle directed to said plurality of memory devices, and

wherein said memory control interface portion receives control signals from said input/output bus and provides control signals to said data buffer to transfer data between said plurality of memory devices and said host bus and to said memory address means to provide address and control signals to said plurality of memory devices based on the address signals on said processor bus and the control signals on said input/output bus when said bus master is directing operation cycles to said plurality of memory devices.