Data processing system and method thereof

• US 5,537,562 A
• Filed: 04/19/1995
• Issued: 07/16/1996
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/424,990
• Time in Patent Office: 454 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/234
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A method of executing an instruction in a data processor, comprising the steps of:

receiving a first instruction;

decoding the first instruction to provide a first plurality of control signals;

accessing an enable value from an enabled one of a plurality of processing elements in response to a first portion of the plurality of control signals, the enable value selectively enabling the enabled one of a plurality of processing elements to participate in execution of an instruction;

accessing a history value from the enabled one of a plurality of processing elements in response to a second portion of the plurality of control signals; and

selectively modifying the enable value in response to a logic state of the history value.

2. The method of claim 1 further comprising the steps of:

accessing a plurality of enable values from each of an enabled portion of the plurality of processing elements in response to a first portion of the plurality of control signals, each of the plurality of enable values selectively enabling a corresponding one of the plurality of processing elements to participate in execution of an instruction;

accessing a plurality of history values from each of the enabled portion of the plurality of processing elements in response to a second portion of the plurality of control signals, each of the plurality of history values corresponding to one of the enabled portion of the plurality of processing elements; and

selectively modifying each of the plurality of enable values in response to a logic state of a corresponding one of the plurality of history values.

3. The method of claim 1 wherein the first instruction has a mnemonic form of "velse".

4. The method of claim 1 wherein the step of selectively modifying further comprising the steps of:

complementing the first one of the plurality of enable values when a corresponding one of the plurality of history values is in a first logic state; and

negating the first one of the plurality of enable values when the corresponding one of the plurality of history values is in a second logic state.

5. The method of claim 1 further comprising the step of:

asserting a first one of the plurality of history values when a corresponding one of the plurality of enable values is in an asserted logic state.

6. The method of claim 5 the corresponding one of the plurality of enable values is in the asserted logic state to indicate that a condition of a previously executed instruction has been met.

7. The method of claim 5 wherein the corresponding one of the plurality of enable values is in the negated logic state to indicate that a condition of a previously executed instruction has not been met.

8. The method of claim 1 wherein the first instruction is executed subsequent to execution of a second instruction, a method for executing the second instruction comprising the steps of:

receiving a second instruction;

decoding the second instruction to provide a second plurality of control signals;

accessing the enable value from a processing element in response to a first portion of the second plurality of control signals;

selectively enabling the processing element to participate in execution of the second instruction when the enable value is in an asserted state;

executing a comparison operation in response to a second portion of the plurality of control signals, the processing element being used during execution of the comparison operation when the processing element is enabled to participate; and

selectively negating the enable value corresponding to the processing element when the processing element is enabled to participate, the enables value being negated when the condition of the comparison operation has not been met.

9. The method of claim 8 further comprising the steps of:

accessing the plurality of enable values from each of a plurality of processing elements in response to a first portion of the second plurality of control signals;

selectively enabling a portion of the plurality of processing elements to participate in execution of the second instruction, each of the portion of the plurality of processing elements having an enable value in an asserted state;

executing a comparison operation in response to a second portion of the plurality of control signals, each of the portion of the plurality of processing elements being used during execution of the comparison operation; and

selectively negating each of a portion of the plurality of enable values corresponding to the portion of the plurality of processing elements when the condition of the comparison operation has not been met.

10. The method of claim 1 further comprising the steps of:

receiving a third instruction;

decoding the third instruction to provide a third plurality of control signals;

asserting each of the plurality of enable values; and

negating each of the plurality of history values.

11. The method of claim 10 wherein the third instruction has a mnemonic form of "vendif".

12. The method of claim 10 wherein the second instruction is one of a set of instructions having a mnemonic form of "vif".

13. A data processor, comprising:

storage means for storing a first instruction;

instruction decoding means for decoding the first instruction to provide a first plurality of control values, the instruction decode means being coupled to the storage means for

receiving the first instruction;

a processing element for storing a digital data value;

a first storage circuit for storing an enable value, the enable value corresponding to the processing element, the enable value selectively enabling the processing element to participate in execution of an instruction;

a second storage circuit for storing a history value, the history value corresponding to the processing element, the history value being used to selectively modify the enable value; and

a modification circuit for selectively modifying the enable value in response to a logic state of the history value, the modification circuit being coupled to both the first storage circuit and the second storage circuit.

14. The data processor of claim 13, further comprising:

a plurality of processing elements for storing a plurality of digital data values.

15. The data processor of claim 14 wherein the first storage circuit stores a plurality of enable values, each of the plurality of enable values corresponds to one of the plurality of processing elements and each of the plurality of enables values selectively enables a corresponding one of the plurality of processing elements to participate in execution of an instruction.

16. The data processor of claim 15 wherein the second storage circuit stores a plurality of history values, each of the plurality of history values corresponds to one of the plurality of processing elements and each of the plurality of history values is used to selectively modify a corresponding one of the plurality of enable values.

17. The data processor of claim 16 wherein the modification circuit selectively modifies each of the plurality of enable values in response to a logic state of a corresponding one of a plurality of history values.

18. The data processor of claim 17 wherein the first instruction is used to execute an ELSE portion of an IF, ELSE programming construct.

19. The data processor of claim 17 wherein the modification circuit complements a first one of the plurality of enable values when the corresponding one of the plurality of history bits is in a first logic state and the modification circuit negates the first one of the plurality of enable values when the corresponding one of the plurality of history values is in a second logic state.

20. The data processor of claim 17 wherein a first one of the plurality of history values is asserted when a corresponding one of the plurality of enable values is in an asserted logic state.

21. The data processor of claim 17 wherein a second instruction is executed prior to execution of the first instruction, the second instruction comparing a first one of the plurality of digital data values and a second one of the plurality of digital data values to test a predetermined condition.

23. The data processor of claim 13 wherein a third instruction is executed subsequent to execution of the first instruction, the third instruction asserting each of the plurality of enable values and negating each of the plurality of history value.

22. The data processor of claim 389 Wherein the second instruction negates each of the plurality of enable values stored in the first storage circuit when the predetermined condition is false.