Dynamic memory system having memory refresh
First Claim
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1. A dynamic memory system comprising:
- a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;
a memory refresh circuit coupled to the dynamic memory the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;
a memory address circuit generating a memory address;
a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address;
a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;
a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive a memory address from the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the selected at least one of the dynamic integrated circuit memory chips in response to the received memory address; and
a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips.
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Abstract
An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry. An improved memory architecture is provided that is particularly suitable for dynamic memories and integrated circuit data processors.
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Citations
88 Claims
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1. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a memory address circuit generating a memory address; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive a memory address from the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the selected at least one of the dynamic integrated circuit memory chips in response to the received memory address; and a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12)
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11. A dynamic memory system comprising:
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a dynamic memory for storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and to the memory address circuit and read accessing a plurality of digital data bits in the dynamic memory in response to the memory address; a second access circuit coupled to the first access circuit and to the second clock circuit, the second access circuit operating in response to the second clock signal to read access one of the plurality of digital data bits read accessed in the dynamic memory by the first access circuit; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A dynamic memory system comprising:
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a dynamic memory storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period, said second clock period being shorter than the first clock period of the first clock signal; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and to the memory address circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed by the first access circuit; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by dynamic memory. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A dynamic memory system comprising:
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a dynamic memory for storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal; a memory address circuit that is coupled to the first clock circuit and generates a memory address in response to the first clock signal; a first access circuit that is coupled to the dynamic memory and to the memory address circuit and accesses a plurality of digital data bits in the dynamic memory in response to the memory address; a second access circuit that is coupled to the first access circuit and to the second clock circuit and operates in response to the second clock signal to access in sequence at least two of the plurality of digital data bits accessed by the first access circuit; and a memory refresh circuit that is coupled to the dynamic memory and refreshes the digital data bits stored by the dynamic memory. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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31. A dynamic memory system comprising:
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a dynamic memory for storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address; a first access circuit coupled to the dynamic memory and to the first address decoder circuit and accessing a plurality of digital data bits from the dynamic memory in response to the first decoded signals; a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address; a second access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital bits stored by the dynamic memory. - View Dependent Claims (32, 33, 34, 35)
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36. A dynamic memory system comprising:
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a dynamic memory adapted to store digital data bits; a first memory address circuit generating a first memory address; a first address decoder circuit coupled to the first memory address circuit, the first address decoder circuit generating first decoded signals in response to the first memory address; a first access circuit coupled to the first address decoder circuit and to the dynamic memory, the first access circuit accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals; a second memory address circuit generating a second memory address; a second address decoder circuit coupled to receive the second memory, address from the second memory address circuit, the second address decoder circuit generating second decoded address signals in response to the second memory address; a second access circuit coupled to the first access circuit and coupled to receive the second decoded address signals from the second address decoder circuit, the second access circuit operating in response to the second decoded address signals to select one of the plurality of digital data bits accessed by the first access circuit; an output circuit coupled to receive the selected digital data bit from the second access circuit, the output circuit outputting the selected digital data bit; and a refresh circuit coupled to the dynamic memory, the refresh circuit refreshing the digital data bits stored by the dynamic memory. - View Dependent Claims (37, 38, 39, 40)
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41. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a memory address circuit generating a memory address; a decoder circuit coupled to receive a memory address from the memory address circuit and generating memory chip select signals in response to the received memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address; and a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit memory chips. - View Dependent Claims (42, 43, 44, 45, 46, 47)
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48. A dynamic memory system comprising:
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a dynamic memory storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; a refresh address counter generating a refresh address; and a memory refresh circuit coupled to the dynamic memory and to the refresh address counter and refreshing the digital data bits stored by the dynamic memory in response to the refresh address. - View Dependent Claims (49)
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50. A dynamic random access memory system comprising:
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a dynamic memory for storing a plurality of digital data bits; a first clock circuit generating a first clock signal; a second clock circuit generating a second clock signal; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the memory address; a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and accessing a plurality of the digital data bits randomly accessed in the dynamic memory by the first access circuit in response to the second clock signal; a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; and an output circuit coupled to the second access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit. - View Dependent Claims (51)
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52. A dynamic memory system comprising:
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a dynamic memory storing data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a first clock circuit generating a first clock signal; a second clock circuit generating a second clock signal; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the first memory accessing circuit randomly accessing a plurality of data bits stored by the dynamic memory in response to the memory address; a shift register circuit coupled to the first memory accessing circuit the shift register circuit outputting a one bit wide sequence of the plurality of data bits random accessed by the first memory accessing circuit; and a second accessing circuit coupled to the first memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the first memory accessing circuit. - View Dependent Claims (53)
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54. A dynamic memory system comprising:
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a dynamic memory storing data bits; a first clock circuit generating a first clock signal; a memory address circuit coupled to the first clock circuit, the memory address circuit generating a memory address in response to the first clock signal; a second clock circuit generating a second clock signal; a first memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the first memory address circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit; a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a sequence of the plurality of data bits accessed by the memory accessing circuit; a refresh address counter circuit generating a refresh address; and a memory refresh circuit coupled to the refresh address counter circuit and to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory in response to the refresh address. - View Dependent Claims (55)
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56. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips each dynamic integrated circuit memory chip storing a plurality of digital data bits; a first clock circuit generating a first clock signal; a second clock circuit generating a second clock signal; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit accessed by the second access circuit from a selected one of the plurality of dynamic integrated circuit memory chips as a memory output signal on a conductor that is common to the plurality of dynamic integrated circuit memory chips. - View Dependent Claims (57)
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58. A dynamic memory system comprising:
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a dynamic memory for storing a plurality of digital data bits; a first clock circuit generating a first clock signal having a first clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a second clock circuit generating a second clock signal having a second clock period; a memory access circuit coupled to the dynamic memory and to the memory address circuit and accessing a plurality of digital data bits stored by the dynamic memory in response to the memory address; and a selection circuit coupled to the memory access circuit and to the second clock circuit and operating in response to the second clock signal to select at least one but not all of the digital data bits accessed in the dynamic memory by the memory access circuit.
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59. A dynamic memory system comprising:
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a dynamic memory for storing digital data bits including instruction digital data bits and operand digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and to the memory address circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit; and a memory refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing digital data bits stored by the dynamic memory in response to the processing of the digital data bit by the stored program computer.
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60. A dynamic memory system comprising:
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a dynamic memory storing a plurality of digital data bits; a first clock circuit generating a first clock signal; a second clock circuit generating a second clock signal; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit, the first access circuit accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal; a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and accessing a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal; a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; and an output circuit coupled to the second access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit.
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61. A dynamic memory system comprising:
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a dynamic memory storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and coupled to receive the memory address and accessing a plurality of digital data bits in the dynamic memory in response to the memory address; a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access a plurality of the digital data bits accessed in the dynamic memory by the first access circuit; an output shifting circuit coupled to the multiple digital data bit access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit; and a display monitor coupled to the output shifting circuit and displaying data in response to the plurality of digital data bits output by the output shifting circuit.
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62. A dynamic random access memory system comprising:
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a dynamic memory storing digital data bits including instruction digital data bits and operand digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the memory address; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits randomly accessed in the dynamic memory by the first access circuit; a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit; a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing the digital data bits stored by the dynamic memory in synchronization with the processing of the operand digital data bit by the stored program computer.
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63. A dynamic memory system comprising:
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a dynamic memory storing digital data bits in a plurality of pages of dynamic memory; a paging logic circuit coupled to the plurality of pages of dynamic memory to select one of the plurality of pages of dynamic memory; a first clock circuit generating a first clock signal having a first a clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic memory, to the memory address circuit, to the first clock circuit, and to the paging logic circuit, the first access circuit operating in response to the memory address and in response to the first clock signal to access a plurality of digital data bits from the page of dynamic memory selected by the paging logic circuit; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.
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64. A dynamic memory system comprising;
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a dynamic main memory storing a plurality of digital data bits including instruction digital data bits and operand digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic main memory, to the memory address circuit, and to the first clock circuit, the first access circuit accessing a plurality of digital data bits in the dynamic main memory in response to the memory address and in response to the first clock signal; a second access circuit coupled to the first access circuit and to the second clock circuit, the second access circuit operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic main memory by the first access circuit; a memory refresh circuit coupled to the dynamic main memory and refreshing the instruction digital data bits and the operand digital data bits stored by the dynamic main memory; and a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit.
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65. A dynamic memory system comprising:
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a plurality of pages of dynamic memory storing digital data bits; a paging logic circuit generating a page select signal to select one of the plurality of pages of dynamic memory; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic memory, to the memory address circuit, to the first clock circuit, and to the paging logic circuit, the first access circuit operating in response to the memory address, in response to the first clock signal, and in response to the page select signal to access a plurality of digital data bits in the page of dynamic memory selected by the paging logic; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.
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66. A dynamic memory comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each said dynamic integrated circuit memory chip storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal; a memory address circuit for generating a memory address; a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed by the first access circuit; a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; a decoder circuit coupled to the memory address circuit and generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit accessed by the second access circuit in a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips.
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67. A dynamic random access memory system comprising:
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a dynamic memory for storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits from the dynamic memory in response to the memory address; a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access a plurality of the digital data bits randomly accessed in the dynamic memory by the first access circuit; an output shifting circuit coupled to the multiple digital data bit access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit; and a display monitor coupled to the output shifting circuit and displaying data in response to the plurality of digital data bits output by the output shifting circuit.
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68. A dynamic random access memory system implemented on a single integrated circuit chip comprising:
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a dynamic memory for storing digital data bits, wherein the dynamic memory is implemented on the single integrated circuit chip; a first clock circuit generating a first clock signal having a first clock period, wherein the first clock circuit is implemented on the single integrated circuit chip; a second clock circuit generating a second clock signal having a second clock period, wherein the second clock circuit is implemented on the single integrated circuit chip; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal, wherein the memory address circuit is implemented on the single integrated circuit chip; a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the memory address, wherein the first access circuit is implemented on the single integrated circuit chip; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits that were randomly accessed in the dynamic memory by the first access circuit, wherein the second access circuit is implemented on the single integrated circuit chip; a refresh address counter generating a refresh address, wherein the refresh address counter is implemented on the single integrated circuit chip; and a memory refresh circuit coupled to the dynamic memory and to the refresh address counter and refreshing the digital data bits stored by the dynamic memory in response to the refresh address, wherein the memory refresh circuit is implemented on the single integrated circuit chip.
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69. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal; a memory address circuit generating a memory address; a decoder circuit coupled to the memory address circuit and generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a first access circuit coupled to the dynamic memory and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the first clock signal; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access in sequence at least two of the plurality of digital data bits in sequence accessed by the first access circuit; a plurality of memory output circuits coupled to the second access circuit and sequentially outputting the at least two of the plurality of digital data bits accessed by the second access circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit memory chips; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.
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70. A dynamic memory system comprising:
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a dynamic memory storing digital data bits in a plurality of pages of dynamic memory; a paging logic circuit generating a page select signal to select one of the plurality of pages of dynamic memory; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal; a memory address circuit generating a memory address; a first access circuit coupled to the dynamic memory to the memory address circuit, to the first clock circuit and to the paging logic and accessing a plurality of digital data bits in the page of dynamic memory that is selected by the paging logic in response to the memory address and in response to the first clock signal; a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access in sequence at least two of the plurality of digital data bits accessed by the first access circuit; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.
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71. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit that is coupled to the first clock circuit and generates a memory address in response to the first clock signal; a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address; a first access circuit coupled to the dynamic memory and to the first address decoder circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the first clock signal and the first decoded signals; a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address; a second access circuit coupled to the first access circuit, to the second clock circuit and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to randomly access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits; a memory refresh circuit coupled to the dynamic memory and refreshing the digital bits stored by the dynamic memory; a chip decoder circuit coupled to the memory address circuit and generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the chip decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit accessed by the second access circuit in a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit memory chips.
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72. A dynamic memory system comprising:
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a dynamic memory for storing digital data bits; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address; a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address; a first access circuit coupled to the dynamic memory and to the first address decoder circuit and randomly accessing a plurality of digital data bits from the dynamic memory in response to the first clock signal; a multiple digital data bit access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and accessing a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal and the second decoded signals; an output circuit coupled to the multiple digital data bit access circuit and outputting the plurality of digital data bits accessed by the multiple digital data bit access circuit; a memory refresh circuit coupled to the dynamic memory and refreshing the digital bits stored by the dynamic memory; and an output shifting circuit coupled to the multiple digital data bit access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit.
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73. A dynamic memory system comprising:
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a dynamic memory storing digital data bits in a plurality of pages of dynamic memory; a first clock circuit generating a first clock signal having a first clock period; a second clock circuit generating a second clock signal having a second clock period; a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal; a first address decoder circuit that is coupled to the memory address circuit and generates first decoded signals in response to a first part of the memory address; a paging logic circuit generating a page select signal to select one of the plurality of pages of dynamic memory; a first access circuit coupled to the dynamic memory, to the first address decoder circuit, and to the paging logic circuit and operating in response to the first decoded signals and in response to the page select signal to access a plurality of digital data bits in the page of dynamic memory that is selected by the paging logic; a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address; a second access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to access one of the plurality of digital data bits accessed by the first access circuit; an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits; and a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.
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74. A dynamic memory system comprising:
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a dynamic memory including a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a first memory address circuit generating a first memory address; a first address decoder circuit coupled to receive the first memory address from the first memory address circuit and generate first decoded signals in response to the first memory address; a first access circuit coupled to receive the first decoded signals from the first address decoder circuit and coupled to the dynamic memory, the first access circuit random accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals; a second memory address circuit generating a second memory address; a second address decoder circuit coupled to receive the second memory address from the second memory address circuit and generate second decoded signals in response to the second memory address; a second access circuit coupled to the first access circuit and coupled to receive the second decoded signals from the second address decoder circuit, the second access circuit operating in response to the second decoded signals to select one of the plurality of digital data bits accessed by the first access circuit; third memory address circuit generating a third memory address; a third address decoder circuit coupled to receive the third memory address from the third memory address circuit and generate memory chip select signals in response to the third memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive the memory chip select signals from the third address decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a memory output signal conductor coupled to each of the dynamic integrated circuit memory chips; a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit selected by the second access circuit from the selected at least one of the plurality of dynamic integrated circuit memory chips onto the memory output signal conductor; and a refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.
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75. A dynamic memory system comprising:
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a dynamic memory adapted to store digital data bits; a first memory address circuit generating a first memory address; a first address decoder circuit coupled to the first memory address circuit, the first address decoder circuit generating first decoded signals in response to the first memory address; a first access circuit coupled to the first address decoder circuit and to the dynamic memory, the first access circuit accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals; a second memory address circuit generating a second memory address; a second address decoder circuit coupled to the second memory address circuit, the second address decoder circuit generating second decoded signals in response to the second memory address; a multiple digital data bit access circuit coupled to the first access circuit and to the second address decoder circuit, the multiple digital data bit access circuit operating in response to the second decoded signals to select a plurality of the digital data bits accessed by the first access circuit; an output circuit coupled to the multiple digital data bit access circuit, the output circuit outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit; and a refresh circuit coupled to the dynamic memory, the refresh circuit refreshing the digital data bits stored by the dynamic memory.
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76. A dynamic memory system comprising:
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a dynamic memory adapted to store digital data bits; a first address circuit generating a first memory address; a first address decoder circuit coupled to receive the first memory address from the first memory address circuit, the first address decoder circuit generating first decoded signals in response to the first memory address; a first access circuit coupled to receive the first decoded signals from the first address decoder circuit and coupled to the dynamic memory, the first access circuit accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals; a second memory address circuit generating a second memory address; a second address decoder circuit coupled to receive the second memory address from the second memory address circuit, the second address decoder circuit generating second decoded signals in response to the second memory address generated by the second memory address circuit; a second access circuit coupled to receive the plurality of digital data bits accessed by the first access circuit and coupled to receive the second decoded signals from the second address decoder circuit, the second access circuit operating in response to the second decoded signals to select one of the plurality of digital data bits accessed by the first access circuit; an output circuit coupled to the second access circuit, the output circuit outputting the selected digital data bit; a refresh address counter generating a refresh address; and a memory refresh circuit coupled to receive a refresh address from the refresh address counter, the memory refresh circuit refreshing the digital data bits stored by the dynamic memory in response to the refresh address.
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77. A dynamic memory system comprising:
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a dynamic memory storing data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a memory address circuit generating a memory address; a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; and a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a bit serial sequence of the plurality of data bits accessed by the memory accessing circuit.
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78. A dynamic memory system comprising:
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a dynamic memory storing data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a memory address circuit generating a memory address; a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; a shift register circuit coupled to the memory accessing circuit, the shift register circuit storing and outputting a sequence of the plurality of data bits accessed by the memory accessing circuit; and a refreshable display coupled to the shift register circuit, the refreshable display generating a refreshed image in response to the sequence of data bits generated and outputted by the shifting circuit.
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79. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a memory address circuit generating a memory address; a memory accessing circuit coupled to the dynamic memory and coupled to receive the memory address from the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; a shift register circuit coupled to the memory accessing circuit, the shift register circuit storing and outputting a sequence of the plurality of data bits accessed by the memory accessing circuit; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and a plurality of memory output circuits coupled to the memory accessing circuit, each memory output circuit outputting at least one of the data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips as a memory output signal on a conductor common to the plurality of dynamic integrated circuit memory chips.
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80. A dynamic memory system comprising:
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a dynamic memory storing a plurality of data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a first clock circuit generating a first clock signal; a second clock circuit generating a second clock signal; a memory address circuit coupled to the first clock circuit, the memory address circuit generating a memory address in response to the first clock signal; a first address decoder circuit coupled to the memory address circuit, the first address decoder circuit generating first decoded signals in response to a first part of the memory address; a second accessing circuit coupled to the dynamic memory and to the first address decoder circuit, the second accessing circuit accessing the plurality of data bits from the dynamic memory in response to the first decoded signals; a second address decoder circuit coupled to the memory address circuit, the second address decoder circuit generating second decoded signals in response to a second part of the memory address; a third accessing circuit coupled to a memory accessing circuit, to the second clock circuit, and to the second address decoder circuit, the third accessing circuit operating in response to the second clock signal and the second decoded signals to access one of the plurality of data bits accessed by the memory accessing circuit; an output circuit coupled to the second accessing circuit, the output circuit outputting the accessed one of the plurality of data bits; the memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; and a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a sequence of the plurality of data bits accessed by the memory accessing circuit.
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81. A dynamic memory system comprising:
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a dynamic memory storing data bits a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a memory address circuit generating a memory address; a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing from the dynamic memory a plurality of data bits stored by the dynamic memory in response to the memory address; a shift register circuit coupled to the memory accessing circuit, the shift register circuit shifting out a sequence of the plurality of data bits accessed by the memory accessing circuit; a first clock circuit generating a first clock signal, wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal; a second clock circuit generating a second clock signal; a multiple data bit accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the multiple data bit accessing circuit operating in response to the second clock signal to access a plurality of the data bits accessed from the dynamic memory by the memory accessing circuit; and an output shifting circuit coupled to the second accessing circuit, the output shifting circuit outputting a sequence of the plurality of data bits accessed by the multiple data bit accessing circuit.
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82. A dynamic memory system comprising:
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a dynamic memory storing data bits including instruction data bits and operand data bits; a memory address circuit generating a memory address; a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; a shift register circuit coupled to the memory accessing circuit, the shift register circuit shifting out a sequence of the plurality of data bits accessed by the memory accessing circuit; a first clock circuit generating a first clock signal; a second clock circuit generating a second clock signal; the memory address circuit being coupled to the first clock circuit, the memory address circuit generating the memory address in response to the first clock signal; a second accessing circuit coupled to the memory accessing circuit and to the second clock signal, the second accessing circuit accessing one of the plurality of data bits accessed by the memory accessing circuit; a stored program computer coupled to the second accessing circuit, the stored program computer processing an operand data bit accessed by the second accessing circuit in response to an instruction data bit accessed by the second accessing circuit; and a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory, the synchronized refresh circuit refreshing the data bits stored by the dynamic memory in synchronization with the processing of the data bit by the stored program computer.
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83. A dynamic memory system comprising:
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a dynamic memory including a plurality of pages of dynamic memory storing data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a memory address circuit generating a memory address; a paging logic circuit generating a page select signal that is coupled to each of the plurality of pages of dynamic memory and selects one of the plurality of pages of dynamic memory; a memory accessing circuit coupled to the dynamic memory and to the paging logic circuit, the memory accessing circuit accessing a plurality of digital data bits from the page of dynamic memory that is selected by the paging logic in response to the memory address; and a shift register circuit coupled to receive the plurality of data bits from the memory accessing circuit, the shift register circuit shifting out a sequence of the plurality of data bits accessed by the memory accessing circuit.
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84. A dynamic memory system comprising:
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a dynamic main memory storing instruction data bits and operand data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory; a memory address circuit generating a memory address; a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a sequence of the plurality of data bits accessed by the memory accessing circuit; and a stored program computer coupled to the memory accessing circuit, the stored program computer processing an operand data bit accessed by the memory accessing circuit in response to an instruction data bit accessed by the memory accessing circuit.
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85. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a memory address circuit generating a memory address; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the selected at least one of the dynamic integrated circuit memory chips in response to the memory address; a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips; a shift register coupled to the memory accessing circuit, the shift register outputting a serial sequence of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips; and a refreshable display coupled to the shift register, the refreshable display generating a refreshed image in response to the serial sequence of the plurality of data bits.
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86. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a first clock circuit generating a first clock signal; a memory address circuit coupled to the first clock circuit, the memory address circuit generating a memory address in response to the first clock signal; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select, signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address; a second clock circuit generating a second clock signal; a multiple data bit accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the multiple data bit accessing circuit operating in response to the second clock signal to access a plurality of the data bits that were accessed from the dynamic memory by the memory accessing circuit; a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips; and an output shifting circuit coupled to the multiple data bit accessing circuit, the output shifting circuit outputting a sequence of the plurality of data bits accessed by the multiple data bit accessing circuit.
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87. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a memory address circuit generating a memory address; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory address; a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit and accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address; a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips; a shift register coupled to the memory accessing circuit, the shift register outputting a serial sequence of the plurality of data bits accessed by the memory accessing circuit from the selected one of the plurality of dynamic integrated circuit memory chips; and a refreshable display coupled to the shift register, the refreshable display generating a refreshed image in response to the serial sequence of the plurality of data bits.
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88. A dynamic memory system comprising:
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a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory, and refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a first clock circuit generating a first clock signal; a memory address circuit coupled to receive the first clock signal from the first clock circuit and generating a memory address in response to the received first clock signal; a second clock circuit generating a second clock signal; a decoder circuit coupled to receive a memory address from the memory address circuit, the decoder circuit generating memory chip select signals in response to the received memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive memory chip select signals from the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the received memory chip select signals; a first memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive a memory address from the memory address circuit, the first memory accessing circuit accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the received memory address; a second memory accessing circuit coupled to the first memory accessing circuit and coupled to receive the second clock signal from the second clock circuit, the second memory accessing circuit operating in response to the received second clock signal to access one of the plurality of data bits accessed by the first memory accessing circuit; and a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips.
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Specification