System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information

• US 5,537,575 A
• Filed: 06/30/1994
• Issued: 07/16/1996
• Est. Priority Date: 06/30/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Foley, Denis, Van Doren, Stephen R., Burns, Douglas J.
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/268,403
• Time in Patent Office: 747 Days
• Field of Search: 395/250, 395/425, 395/400, 395/250, 395/468, 395/471, 395/472, 395/473, 395/486, 364/DIG. 1, 364/DIG. 2
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus. In response to the command for transmitting cache memory victim data, the cache memory data which is waiting in the data interface, is transmitted from the data interface to main memory over the system bus.

Claims

1. In a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol, each of said processor modules including:

a processor, said processor capable of executing a READ of a cache memory coupled to said processor, said cache memory including means for storing cache memory address information, means for storing cache memory data and means for storing cache memory status information, and

a data interface coupled to said system bus and to said means for storing said cache memory data,

a method of processing cache memory victim data for updating said main memory, comprising the steps of;

upon said processor executing said READ of said cache memory address information, simultaneously transmitting cache memory data corresponding to said cache memory address information into said data interface from said means for storing cache memory data;

receiving said cache memory data accumulatively by said data interface during the execution of said READ of said cache memory address information;

determining if said cache memory data corresponding to said cache memory address information being READ is a cache memory victim by using the cache memory status information;

if said determining establishes that said cache memory data corresponding to said cache memory address information being READ is a cache memory victim, causing said processor to issue a command for transmitting cache memory victim data to said main memory over said system bus; and

transmitting, from said data interface to said main memory over said system bus, in response to said command for transmitting cache memory victim data, said cache memory data corresponding to said cache memory address information being READ.

2. The method of processing cache memory victim data as set forth in claim 1 wherein the step of receiving said cache memory data accumulatively by said data interface includes the step of receiving said cache memory data by a buffer coupled to said system bus and to said means for storing said cache memory data, said buffer capable of receiving, accumulatively during execution of said READ, said cache memory data, and of transmitting to said system bus said cache memory data received by said buffer.

3. The method of processing cache memory victim data as set forth in claim 2 wherein said step of determining if said cache memory data corresponding to said cache memory address being READ is a cache memory victim is performed by evaluating cache memory status information corresponding to said cache memory address information being READ to determine if said cache memory status information corresponding to said cache memory address information being READ indicates a DIRTY status.

4. The method of processing cache memory victim data as set forth in claim 3 wherein the step of causing said processor to issue a command for transmitting cache memory victim data to said main memory over said system bus includes the step of issuing a VICTIM command to the address interface which controls the transmitting of said cache memory victim data to said main memory over said system bus.