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Synchronized fault tolerant reset

  • US 5,537,655 A
  • Filed: 11/21/1994
  • Issued: 07/16/1996
  • Est. Priority Date: 09/28/1992
  • Status: Expired due to Term
First Claim
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1. A synchronizing circuit comprising a plurality of modules for receiving respective asynchronous input signals and respective local clock signals, each module comprising:

  • a de-metastabilizer stage for receiving the input signal and the local clock signal of said module and providing a first stage output signal representative of the input signal synchronized to the local clock signal, said first stage output signal being free of glitches and metastable conditions,a global synchronizing means for receiving the first stage output signal of the de-metastabilizer stage of each module and the local clock signal of said module and providing respective second stage output signals synchronized to the local clock signal, each second stage output signal being representative of the respective first stage output signal of an associated de-metastabilizer stage as synchronized to the local clock signal of said module, anda majority edge detector and voter network for receiving the second stage output signals of the global synchronizing means of said module and outputting and holding a voted output signal upon receiving from the global synchronizing means of said module a majority of enabling edge transitions of the second stage output signals.

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