Synchronized fault tolerant reset

• US 5,537,655 A
• Filed: 11/21/1994
• Issued: 07/16/1996
• Est. Priority Date: 09/28/1992
• Status: Expired due to Term

• Current Assignee: Rateze Remote Mgmt. L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Boeing Co.
• Inventors: Truong, Tuong K.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/342,763
• Time in Patent Office: 603 Days
• Field of Search: 395/515, 395/200, 395/325, 395/550, 395/182.1, 395/182.21, 307/409, 307/407, 371/3, 371/5.4, 371/42, 371/47.1, 371/61, 371/62, 371/68.1, 371/68.3, 375/106, 375/107, 375/108, 364/950, 364/950.1, 364/950.3
• US Class Current: 714/12
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components

Abstract

A synchronizing circuit comprises a plurality of substantially identical modules for receiving respective asynchronous input signals and respective local clock signals with the local clock signals of the respective modules being substantially synchronized. Each module of the synchronizing circuit comprises a de-metastabilizer stage, a global synchronizing stage and a majority edge detector and voter network. The de-metastabilizer stage receives the input signal of the module and provides an output signal free of glitches and metastable conditions, synchronized to the local clock signal. The global synchronizing stage receives the output signals of the de-metastabilizer stage of each module and provides respective output signals synchronized to the local clock signal. The majority edge detector and voter network receives the output signals of the global synchronizing stage and outputs a voted output signal synchronized to the other modules'"'"' voted output signals and to the local clock signal.

Claims

1. A synchronizing circuit comprising a plurality of modules for receiving respective asynchronous input signals and respective local clock signals, each module comprising:

a de-metastabilizer stage for receiving the input signal and the local clock signal of said module and providing a first stage output signal representative of the input signal synchronized to the local clock signal, said first stage output signal being free of glitches and metastable conditions,

a global synchronizing means for receiving the first stage output signal of the de-metastabilizer stage of each module and the local clock signal of said module and providing respective second stage output signals synchronized to the local clock signal, each second stage output signal being representative of the respective first stage output signal of an associated de-metastabilizer stage as synchronized to the local clock signal of said module, and

a majority edge detector and voter network for receiving the second stage output signals of the global synchronizing means of said module and outputting and holding a voted output signal upon receiving from the global synchronizing means of said module a majority of enabling edge transitions of the second stage output signals.

2. A synchronizing circuit according to claim 1 wherein the majority edge detector and voter network outputs and holds as said voted output signal one of a high or low voted output signal upon receiving a majority of enabling edge transitions of the second stage output signals received from the global synchronizing means of said module and subsequently outputs and holds the other of said high or low voted output signal upon receiving a majority of disabling edge transitions of the second stage output signals received from the global synchronizing means of said module.

3. A synchronizing circuit according to claim 1 further comprising an isolation buffer network between said de-metastabilizer stage and said global synchronizing means.

4. A synchronizing circuit according to claim 1 further comprising, for each module, means for generating a reset signal to provide the input signal.

5. A synchronizing circuit according to claim 1 wherein said de-metastabilizer stage is a plurality of latches interconnected by an XOR gate and a multiplexer, and said global synchronizing means is a plurality of latches.

6. A synchronizing circuit according to claim 1 wherein said de-metastabilizer synchronizes the input signal to a rising edge of the local clock signal, and said global synchronizing means synchronizes the first stage output signals of said de-metastabilizer to the rising edge of the local clock signal.

7. A synchronizing circuit according to claim 1 wherein each module further comprises third synchronizing means for arming and disarming the majority edge detector and for synchronizing said voted output signal of the majority voter network to the local clock signal.

8. A synchronizing circuit according to claim 1 wherein the majority edge detector and voter network includes:

first lane latching means for providing a first lane latched output signal for each second stage output signal, each first lane latched output signal being latched in a first state when the corresponding second stage output signal transitions from a first state to a second state, each first lane latched output signal that has been latched into said first state remaining in said first state until cleared by a voted reset output signal; and

first lane majority voting means for providing said voted reset output signal synchronous with the local clock signal and in accordance with a majority of the first lane latched output signals of the first lane latching means.

9. A synchronizing circuit according to claim 8 wherein the majority edge detector and voter network further comprises:

second lane latching means for providing a second lane latched output signal for each second stage output signal, each second lane latched output signal being latched in a first state when the corresponding second stage output signal transitions from its second state to its first state when said voted reset output signal is in a first state, each second lane latched output signal that has been latched into said first state remaining in said first state until cleared by the complement of said voted reset signal; and

second lane majority voting means for clearing said voted reset output signal to a second state in accordance with a majority of the second lane latched output signals of the second lane latching means.

10. A fault tolerant computer system comprising a plurality of modules for receiving respective asynchronous reset signals and respective local clock signals, each module comprising:

a de-metastabilizer stage for firstly synchronizing the reset signal of said module to the local clock signal,

a global synchronizing means for receiving the firstly synchronized reset signal from the de-metastabilizer stage of each of said plurality of modules and secondly synchronizing the firstly synchronized reset signals to the local clock signal,

a majority edge detector and voter network having a plurality of input terminals for receiving the secondly synchronized reset signals from the global synchronizing means of said module, and an output terminal for outputting a voted reset signal representative of the majority of the secondly synchronized reset signals, the majority edge detector and voter network providing said voted reset signal which is held in a given state upon receiving a majority of enabling edge transitions of the secondly synchronized reset signals from the global synchronizing means of said module,

third synchronizing means for arming and disarming the majority edge detector and for synchronizing the voted reset signal to the local clock signal, and

computer means for receiving as inputs the local clock signal and the synchronized voted reset signal.

11. A fault tolerant computer system according to claim 10 wherein the majority edge detector and voter network provides said voted reset signal which is held in one of a high or low state upon receiving a majority of enabling edge transitions of the secondly synchronized reset signals from the global synchronizing means of said module when said voted reset signal is the other of said high or low states and subsequently outputs said voted reset signal which is held in the other of said high or low states upon receiving a majority of disabling edge transitions of the secondly synchronized reset signals from the global synchronizing means of said module when said voted reset signal is the one of said high or low states.

12. A fault tolerant computer system according to claim 10 wherein said third synchronizing means comprises an S/R flip-flop means for providing said synchronized voted reset signal in accordance with the signals received at its S and R inputs as clocked by the local clock;

and

said majority edge detector and voter network comprises first and second lane latching and voting means supplying respective first and second lane voted output signals to the S and R inputs of said S/R flip-flop means, the first lane latching means providing first lane latched output signals, each first lane latched output signal being provided in a first state as latched by a first-to-second state transition of its associated second stage output signal when said synchronized voted reset signal is in a first state and being cleared when said synchronized voted reset signal is in a second state, the first lane voting means receiving said first lane latched output signals and providing a first lane voted output signal in accordance with a majority of said first lane latched output signals, the first lane voted output signal being coupled to one of said S and R inputs of said S/R flip-flop means, the second lane latching means providing second lane latched output signals, each second lane latched output signal being provided in a first state as latched by second-to-first state transitions of its associated second stage output signal when said synchronized voted reset signal is in its second state and being cleared when said synchronized voted reset signal is in its first state, the second lane voting means receiving said second lane latched output signals and providing a second lane voted output signal in accordance with a majority of said second lane latched output signals, the second lane voted output signal being coupled to the other of said S and R inputs of said S/R flip-flop means.