Method and apparatus for a microprocessor to enter and exit a reduced power consumption state

• US 5,537,656 A
• Filed: 06/17/1994
• Issued: 07/16/1996
• Est. Priority Date: 06/17/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mosley, Larry E., Mozdzen, Thomas J.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Travis, John
• Application Number:
  US08/261,456
• Time in Patent Office: 760 Days
• Field of Search: 395/750, 395/375
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A method and apparatus for placing a microprocessor in and out of a reduced power consumption state utilizing system interrupts in a computer system. The method of the present invention intercepts instructions being executed by the processor before placing the processor in a reduced power consumption state. On a request for the processor to exit the reduced power consumption state, the method of the present inventions allows the processor to execute pre-determined resume instructions to wait out any voltage level fluctuations in the processor as it exits the reduced power consumption state, before allowing the processor to continue execution of the instructions intercepted prior to placing the processor in the reduced power consumption state.

Claims

1. A method for enabling a microprocessor to enter and exit a reduced power consumption state without degradation to instructions being executed by said microprocessor prior to entering said reduced power consumption state, said method comprising the steps of:

a) detecting a first System Management Mode interrupt request for said microprocessor to enter said reduced power consumption state;

b) asserting a first signal upon detecting said first System Management Mode interrupt, wherein said signal causes said microprocessor to complete executing instructions pending in said microprocessor;

c) intercepting instructions in said microprocessor'"'"'s instruction pipeline prior to said microprocessor entering said reduced power consumption state;

d) storing said intercepted instructions in said microprocessor;

e) flushing said instruction pipeline, so that instructions pending in said instruction pipeline are not executed as said microprocessor enters said reduced power consumption state;

f) executing a shutdown instruction in said microprocessor, such that said microprocessor enters said reduced power consumption state, wherein said execution of said shutdown instruction causes current levels in said microprocessor to be gradually reduced as said microprocessor enters said reduced power consumption state;

g) executing a resume instruction in said microprocessor as microprocessor exits said reduced power consumption state; and

h) restoring said intercepted instructions to said microprocessor upon said microprocessor exiting said reduced power consumption state.

4. The method of claim 1 wherein said step (g) further includes the step of waiting out voltage fluctuation in said microprocessor as said microprocessor exits said reduced power consumption state.

5. The method of claim 4 wherein said step of waiting out said voltage fluctuations in said microprocessor upon said microprocessor exiting said reduced power consumption state consumes at least two clock cycles.

6. The method of claim 1 wherein said step (e) includes the steps of:

entering a standby mode upon completion of said instruction intercepting step; and

waiting for a second System Management Mode interrupt upon entering said reduced power consumption state.

2. The method of claim I wherein said step (h) includes the step of restoring said intercepted instructions, so that said microprocessor is restored back to a state said microprocessor was in prior to entering said reduced power consumption state.

3. The method of claim I wherein said step (g) includes the step of detecting a second System Management Mode interrupt for said microprocessor to exit said reduced power consumption state.

7. In a computer system having a processing means coupled to peripheral devices, said processing means executing instructions to said peripherals devices, wherein said processing means enters and exits a reduced power consumption state, said computer system comprising:

a shutdown means responsive to a first System Management Mode interrupt for transitioning said processing means to a reduced power consumption state, said shutdown means including shutdown routines which cause current levels in the processing means to be gradually reduced as the processing means enters the reduce power consumption state, said shutdown means coupled to said processing means;

an intercepting means for intercepting instructions being executed in said processing means prior to said processing means entering said reduced power consumption state, said intercepting means coupled to said shutdown means;

a storing means coupled to said shutdown means for storing said intercepted instructions in said processing means, so that said instructions are not executed in said processing means while said processing means is in said reduced power consumption state;

exiting means responsive to a second System Management Mode interrupt for exiting said reduced power consumption state, said exit means includes exit routines which are executed by said processing means when exiting said reduced power consumption state, said exiting means coupled to said processing means; and

a restoring means coupled to said exiting means for restoring instructions intercepted in said processing means prior to said processing means entering said reduced power consumption state.

8. The computer system of claim 7 further including a signal asserting means for asserting a first signal upon said processing means detecting said first System Management Mode interrupt, wherein said processing means begins to enter said reduced power consumption state upon the assertion of said first signal.

9. The computer system of claim 7 further comprising a flushing means for flushing instructions in said processing means instruction pipeline, so that user instructions in said processing means are not executed as a processing means enters said reduced power consumption state.

10. The computer system of claim 7 wherein said exiting means includes the execution of a resume instruction, said resume instruction including resume routines which are executed by said processing means through a wait out period to wait out voltage fluctuation in said processing means as said processing means exits said reduced power consumption state.

11. The computer system of claim 10 wherein said voltage fluctuation wait out period in said processing means consumes at least two clock cycles.

12. The computer system of claim 7 wherein said storing means further includes means for restoring said intercepted instructions in said processing means, so that said processing means begins executing user instructions from a same point said processing means was executing prior to said processing means entering said reduced power consumption state.

13. An apparatus for enabling a microprocessor to enter and exit a reduced power consumption state in a computer system without degradation in instructions being executed by said microprocessor prior to said microprocessor entering said reduced power consumption state, said apparatus comprising:

a shutdown circuit coupled to said microprocessor, said shutdown circuit activated by a first signal upon said microprocessor detecting a first System Management Mode interrupt, wherein said shutdown circuit includes shutdown routine executed by said microprocessor and causing current levels in the microprocessor to be gradually reduced as said microprocessor enters said reduced power consumption state;

a resume circuit coupled to said microprocessor, wherein said resume circuit includes resume routines executed by said microprocessor upon said microprocessor detecting a second System Management Mode interrupt to exit said reduced power consumption state;

wherein said microprocessor deasserts said first signal upon detecting said second System Management Mode interrupt to exit said reduced power consumption state; and

wherein instructions in an instruction pipeline in said microprocessor are intercepted and stored prior to said microprocessor entering said reduced power consumption state.

14. The apparatus of claim 13 wherein said intercepted instructions are restored in said microprocessor upon said microprocessor exiting said reduced power consumption state.

15. The apparatus of claim 13 wherein said resume routines are executed in said microprocessor to wait out voltage fluctuations in said microprocessor as said microprocessor exits said reduced power consumption state, wherein said wait out period consumes at least two clock cycles.

16. The apparatus of claim 13 wherein said shutdown circuit and resume circuit are coupled to microcode in said processor.

17. The apparatus of claim 13 wherein said shutdown circuit and said resume circuit are coupled to an operating system in said computer system.

18. The apparatus of claim 13 wherein said shutdown circuit and said resume circuit are coupled to a system BIOS in said computer system.

19. The apparatus of claim 13 wherein said instruction pipeline in said microprocessor is flushed of said instructions prior to said microprocessor activating said shutdown circuit.

20. The apparatus of claim 13 wherein said stored instructions in said microprocessor are restored in said microprocessor to place said microprocessor in the same state prior to said microprocessor entering said reduced power consumption state.