Digital electronic still-video camera and method of controlling same to reduce power consumption during playback

• US 5,539,455 A
• Filed: 06/05/1995
• Issued: 07/23/1996
• Est. Priority Date: 12/16/1991
• Status: Expired due to Term

• Current Assignee: Fujifilm Corporation (Fujifilm Holdings Corporation)
• Original Assignee: Fuji Photo Film Co Limited (Fujifilm Holdings Corporation)
• Inventors: Makioka, Katsuya
• Primary Examiner(s): Greening, Wendy R.
• Assistant Examiner(s): Vu, Ngoc-Yen, VU, NGOC YEN T
• Application Number:
  US08/465,180
• Time in Patent Office: 414 Days
• Field of Search: 348/220, 348/222, 348/231, 348/232, 348/233, 358/310, 358/312, 358/313, 358/320, 358/321, 358/906, 358/909.1
• US Class Current: 348/222.1
• CPC Class Codes: H04N 1/00129 with a display device, e.g. CRT or LCD monitor with a television apparatus H04N1/00283; arrangements for control of display devices G09G
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 1/2137 with temporary storage before final recording, e.g. in a frame buffer
• CPC Class Codes: H04N 1/2158 using a detachable storage unit
• CPC Class Codes: H04N 2101/00 Still video cameras
• CPC Class Codes: H04N 2201/212 Selecting different recording or reproducing modes, e.g. high or low resolution, field or frame
• CPC Class Codes: H04N 23/651 for reducing power consumption by affecting camera operations, e.g. sleep mode, hibernation mode or power off of selective parts of the camera
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure

Abstract

Power consumption in a still-video camera at playback of pixel data is suppressed. Image data indicative of each pixel is written in a frame memory in synchronization with a prescribed clock frequency (14.32 MHz) in a photographic mode. At the time of playback, a clock signal whose frequency (7.16 MHz) is half that of the clock signal in the photographic mode is applied to each circuit block of the camera. The value of the count in an H-direction address counter for outputting address data in the horizontal direction is doubled in a doubler circuit. Data representing the doubled value of the count is applied to a frame memory as horizontal-direction address data. As a result, the frame memory outputs pixel data that is thinned out every other pixel, and the outputted data is sent to a playback processing circuit.

Claims

1. A video camera having a recording mode in which pixel image data obtained by picking up an image of a subject is stored in storage means and a still image playback mode in which the pixel image data is read from the storage means for playing back a still image, comprising:

reading means which operates on the basis of an address signal for thinning out and reading the pixel image data from the storage means, said reading means including address signal generating means for counting an input clock signal to generate a count value in a horizontal direction and multiplying said count value by a whole-number greater than one to produce said address signal when the still image playback mode is set;

playback processing means for applying still image playback processing to the pixel image data read by said reading means; and

clock signal generating means for generating said input clock signal having a period which is a greater than one whole-number multiple of a period of a clock signal used in the recording mode, and applying said input clock signal to said reading means and said playback processing means, when the still image playback mode is set;

wherein when the still image playback mode is set, said reading means and said playback processing means operate in synchronization with said input clock signal generated by the clock signal generating means.

2. A video camera in accordance with claim 1, further comprising a controller for controlling operation of said reading means, said address signal generating means, said playback processing means and said clock signal generating means.

3. A video camera in accordance with claim 1, wherein said reading means comprises a read/write controller for outputting a read control signal to the storage means.

4. A video camera in accordance with claim 1, wherein said address signal generating means comprises a doubler circuit for multiplying said count value.

5. A video camera in accordance with claim 4, wherein said address signal generating means comprises an H-address counter and an V-address counter, and a selector for selecting between an output of said H-address counter in the recording mode and an output of said doubler circuit in the still image playback mode.

6. A method of controlling a video camera having a recording mode in which pixel image data obtained by picking up an image of a subject is stored in storage means and a still image playback mode in which the pixel image data is read from the storage means for playing back a still image, comprising the steps of:

(a) thinning out and reading pixel image data from the storage means by reading means which operates on the basis of an address signal;

(b) counting an input clock signal in a horizontal direction to generate a count value and multiplying said count value by a whole number greater than one by address signal generating means included in said reading means to produce said address signal when the still image playback mode is set;

(c) applying still image playback processing by playback processing means to the pixel image data read by said reading means;

(d) generating said input clock signal having a period which is a greater than one whole-number multiple of a period of a clock signal used in the recording mode, when the still image playback mode is set; and

(e) applying said input clock signal to said reading means and said playback processing means, when the still image playback mode is set;

wherein when the still image playback mode is set, said thinning out and reading step (a) and said applying step (c) operate in synchronization with said input clock signal generated at said generating step (d).

7. A video camera having a recording mode in which pixel image data obtained by picking up an image of a subject is stored in storage means and a still image playback mode in which the pixel image data is read from the storage means for playing back a still image, comprising:

clock signal generating means for outputting a clock signal having a period which is a greater than one whole-number multiple of a period of a clock signal utilized in the recording mode, when the still image playback mode is set;

reading means for reading from the storage means the pixel image data in increments of mutually adjacent pixels the number of which is said whole-number multiple;

averaging means for averaging said pixel image data incrementally read by said reading means; and

playback means for performing playback processing of the image pixel data averaged by said averaging means, when the still image playback mode is set;

wherein when the still image playback mode is set, said reading means, said averaging means and said playback means operate in synchronization with said clock signal output by said clock signal generating means.

8. A video camera in accordance with claim 7, further comprising a controller for controlling operation of said clock signal generating means, said reading means, said averaging means and said playback means.

9. A video camera in accordance with claims 7, wherein said averaging means includes:

an adder for adding higher-order bits of the pixel image data with lower-order bits of the pixel image data; and

a divider for dividing the data added by said adder.

10. A video camera in accordance with claim 7, further comprising a frequency divider for frequency dividing said clock signal utilized in the recording mode.

11. A video camera in accordance with claim 10, further comprising a selector for selecting between said clock signal frequency divided by said frequency divider in the still image playback mode and said clock signal in the recording mode.

12. A method of controlling a video camera having a recording mode in which pixel image data obtained by picking up an image of a subject is stored in storage means and a still image playback mode in which the pixel image data is read from the storage means for playing back a still image, comprising the steps of:

(a) outputting a clock signal having a period which is a greater than one whole-number multiple of a period of a clock signal, utilized in the recording mode by clock signal generating means, when the still image playback mode is set;

(b) reading pixel image data from the storage means by reading means, in increments of mutually adjacent pixels the number of which is said whole-number multiple;

(c) averaging the pixel data read at said step (b) by averaging means; and

(d) performing playback processing of the pixel image data averaged at said step (c), when the still image playback mode is set;

wherein when the still image playback mode is set, said reading, averaging and performing steps (b)-(d) operate in synchronization with said clock signal outputted at said outputting step (a).

13. A video camera comprising:

image pick-up means, which includes a solid-state image pick-up device for picking up an image of a subject, for outputting image data which represents said image of the subject;

recording means for storing said image data, which is outputted by said image pick-up means, in a storage means;

playback means for reading the image data from said storage means and subjecting said image data to still image reproduction processing and having a recording mode in which said image pick-up means and said recording means are operated and a still image playback mode in which said playback means is operated;

clock-signal generating means capable of generating a clock signal having a comparatively high frequency and a clock signal having a comparatively low frequency, said clock-signal generating means including frequency selecting means for selecting said high frequency when the recording mode is set and for selecting said low frequency when said still image playback mode is set, said high frequency being a greater than one whole-number multiple of said low frequency;

image reducing means, included in said playback means, for reducing the number of pixels of the image represented by the image data read out of said storage means, a reduction ratio being used that is equal to a ratio of said comparatively high frequency to said comparatively low frequency; and

control means for controlling said clock generating circuit means and said image reducing means in such a manner that said clock signal having said comparatively high frequency is selectively outputted from said clock-signal generating circuit means in said recording mode, and said clock signal having said comparatively low frequency is selectively outputted from said clock-signal generating circuit means and said image reducing means becomes active in said still image playback mode;

wherein when said still image playback mode is set, said playback means and said image reducing means operate in synchronization with said low frequency output from said clock-signal generating means.