Method for manufacturing test simulation in electronic circuit design
First Claim
1. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of:
- providing a description of the design of said electronic assembly;
providing pre-determined test and quality information relating to each component in said electronic assembly;
providing a description of a manufacturing test process; and
simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes.
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Accused Products
Abstract
A manufacturing and test simulation method for electronic circuit design integrated with computer aided design tools to provide concurrent engineering of manufacturing and testability aspects of a product concurrent with the functional design of a product. The manufacturing and test simulator (MTSIM) simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and the design for testability. All simulation by the methods of the present invention applies manufacturing and test models down to the component level. The methods of the simulator include a new yield model for boards and MCMs which accounts for the clustering of solder defects. MTSIM models solder faults, manufacturing workmanship faults, component performance faults, and reliability faults. Fault probabilities for the circuit design are estimated based on the component type, the component functionality, and the assembly process used. Up to seven manufacturing test steps can be simulated by MTSIM. Test coverage models will support all commonly used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, selftest, diagnostics, and burn-in. Pareto and iterative "what-if" analysis may be used to locate particular enhancements which most benefit the manufacturability and testability of the product.
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Citations
56 Claims
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1. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of:
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providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; providing a description of a manufacturing test process; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of:
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(a) providing a description of the design of said electronic assembly; (b) providing pre-determined test and quality information relating to each component in said electronic assembly; (c) providing a description of a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps; (d) estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps; (e) assigning the first of said sequential test steps as the current test step; (f) simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes; (g) determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of step (f); (h) assigning the next of said sequential test steps as the current test step; and (h) repeating steps (f) and (g) and (h) for each of said plurality of test steps of said manufacturing test process. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing test process, said method comprising the steps of:
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providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing assembly process, said method comprising the steps of:
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providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; providing a description of a manufacturing test process; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising:
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means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; means for providing information on a manufacturing test process; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes.
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54. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising:
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(a) means for providing information on the design of said electronic assembly; (b) means for providing pre-determined test and quality information relating to each component in said electronic assembly; (c) means for providing information on a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps; (d) means for estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps; (e) means for assigning the first of said sequential test steps as the current test step; (f) means for simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes; (g) means for determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of said stimulating means; (h) means for assigning the next of said sequential test steps as the current test step; and (i) means for activating said simulating means, said determining means, and said second assigning means for each of said plurality of test steps of said manufacturing test process.
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55. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing test process, said system comprising:
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means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
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56. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing assembly process, said system comprising:
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means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; means for providing information on a manufacturing test process; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
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Specification