Jitter/wander reduction circuit for pulse-stuffed, synchronized digital communications

• US 5,539,785 A
• Filed: 07/27/1994
• Issued: 07/23/1996
• Est. Priority Date: 07/27/1994
• Status: Expired due to Term

• Current Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Original Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Inventors: Turner, Michael D., Schneider, Kevin W., Burch, Richard A.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/281,461
• Time in Patent Office: 727 Days
• Field of Search: 375/362, 375/363, 375/371, 375/373, 375/374, 375/375, 370/105.3, 370/102, 370/100.1, 370/105.1, 370/102, 328/55, 328/72, 327/2, 327/146, 327/91, 327/94, 327/141, 327/155, 377/48
• US Class Current: 375/371
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH

Abstract

A jitter/wander reduction circuit is provided for a desynchronizer deriving an output clock signal from an independent clock signal and phase adjustment signals. Phase adjustment signals relate to a deviation of the independent clock signal from an input clock signal. The circuit includes a frequency offset estimation circuit receiving phase adjustment signals and providing a frequency offset estimation signal. A phase controller receives the frequency offset estimation signal, provides a feedback signal to the frequency offset estimation circuit, and provides a phase difference signal. A clock generator circuit receives the independent clock signal and the phase difference signal. The independent clock signal is adjusted based on the phase difference signal to provide an output clock signal.

Claims

1. A jitter and wander reduction circuit for a receiver deriving an output clock signal from an independent clock signal, and phase adjustment signals relate to a deviation of said independent clock signal from an input clock signal, comprising:

a frequency offset estimation circuit receiving said phase adjustment signals and providing a frequency offset estimation signal;

a phase controller receiving said frequency offset estimation signal and providing a feedback signal to said frequency offset estimation circuit, and a phase difference signal; and

a clock generator circuit receiving said independent clock signal and said phase difference signal, said independent clock signal being adjusted based on said phase difference signal to provide an output clock signal.

2. A jitter and wander reduction circuit according to claim 1, wherein said frequency offset estimation circuit comprises:

a first sample/hold circuit having as inputs a frame synchronization signal and said phase adjustment signals, said sample/hold circuit obtaining a new phase adjustment signal with each frame;

an averaging circuit coupled to said sample/hold circuit for averaging said new phase adjustment signal with a previous phase adjustment signal to provide averaged phase adjustment signals;

an accumulator receiving said averaged phase adjustment signals and providing as an output a net phase adjustment signal count;

a counter receiving said frame synchronization signal and providing as an output a frame count;

a trigger circuit having as an input said net phase adjustment signal count and providing as an output a trigger signal;

a second sample/hold circuit for sampling said net phase adjustment signal count in response to said trigger signal and providing as an output a sampled net phase adjustment signal count;

a third sample/hold circuit for sampling said frame count in response to said trigger signal and providing as an output a sampled frame count;

a summation circuit for adding said sampled net phase adjustment signal count to said feedback signal from said phase controller to provide as an output an adjusted phase adjustment signal count; and

a divider circuit for dividing said adjusted phase adjustment signal count by said sampled frame count to provide said frequency offset estimate signal.

3. A jitter and wander reduction circuit according to claim 2, wherein said phase controller comprises:

a phase accumulator having as an input said frequency offset estimate signal, said phase accumulator accumulating said frequency offset estimate signals received from said frequency offset estimation circuit and providing an overflow signal output;

a logic circuit which receives said overflow signal output and provides as an output said phase difference signal; and

a residual accumulator receiving said phase difference signal, said trigger signal, and said sampled net phase adjustment signal count and providing as an output said feedback signal.

4. A jitter and wander reduction circuit according to claim 3, wherein said residual accumulator comprises:

a summation circuit having as a first input said phase different signal;

a switch activated via said trigger signal to couple said sampled net phase adjustment signal count as a second input to said summation circuit; and

an output accumulator receiving an output from said summation circuit and providing as an output said feedback signal.

5. A jitter and wander reduction circuit according to claim 4, wherein said feedback signal is a residual signal, said residual signal being filtered through an amplifier in a feedback path before being received by said frequency offset estimation circuit.

6. A jitter and wander reduction circuit according to claim 3, wherein said trigger circuit outputs its trigger signal to sample said accumulator and said counter in said frequency offset estimation circuit when a threshold value is reached.

7. A jitter and wander reduction circuit according to claim 6, wherein said threshold value is initially set as a small value.

8. A jitter and wander reduction circuit according to claim 7, wherein said threshold value increases in accordance with a threshold adaptation algorithm.

9. A jitter and wander reduction circuit according to claim 3, wherein said clock generator circuit comprises:

a clock pulse deleter receiving said independent clock signal and a pulse deletion signal and providing as an output a deleted clock signal;

a deletion signal generating logic circuit which receives as an input said phase difference signal and provides as an output said pulse deletion signal; and

a frequency divider receiving said deleted clock signal and providing as an output said output clock signal.

10. A jitter and wander reduction circuit according to claim 9, wherein said receiver is a high speed data service loop receiver having a clock signal as said independent clock signal, and wherein said phase adjustment signals are binary signals indicating whether step function phase adjustments of said input clock signal were added to a digital data frame transmitted across a loop to said receiver.

11. A jitter and wander reduction circuit according to claim 10, wherein said frequency estimation circuit further comprises:

a first multiplier coupled between said accumulator and said second sample/hold circuit; and

a second multiplier coupled between said counter and said third sample/hold circuit.

12. A method for complying with maximum time interval error specifications for an output clock signal derived from received frame information transmitted over a digital data communications link, comprising the steps of:

(a) forming a frequency offset estimate using received stuff signals from said frame information;

(b) providing said frequency offset estimate to a phase controller circuit;

(c) locking said output clock signal via said phase controller circuit to said received stuff signals by using residual phase information from said phase controller circuit in step (a); and

(d) signalling a clock generator circuit from said phase controller circuit to advance or retard the phase of said output clock signal based on said frequency offset estimate.