Method and apparatus for dynamically linking code segments in real time in a multiprocessor computing system employing dual buffered shared memory

• US 5,539,896 A
• Filed: 01/03/1994
• Issued: 07/23/1996
• Est. Priority Date: 11/01/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lisle, Ronald J.
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): Choules, Jack M.
• Application Number:
  US08/176,337
• Time in Patent Office: 932 Days
• Field of Search: 395/600, 395/425, 395/250, 395/375, 395/650, 395/800, 395/873, 395/474, 395/475, 395/477, 395/480, 364/132, 364/221.4, 364/221.8, 364/228, 364/228.1, 364/228.6, 364/239.4, 364/246.3, 364/262.4, 364/262.5, 364/270
• US Class Current: 711/150
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
• CPC Class Codes: G10H 7/004 with one or more auxiliary processor in addition to the main processing unit

Abstract

A system is provided including a host processor and an audio capture and playback adapter having a DSP co-processor. The adapter includes shared memory accessible from both the DSP and the host. A DSP program is periodically written to the shared memory by the host and executed by the DSP. A non ping-pong dual buffer technique is disclosed wherein alternately one buffer is executed by the DSP while the remaining buffer is updated or linked by the host. In one embodiment, two pointer variables are used, each indicating respectively which buffer is currently being executed by the DSP and which has been updated by the host. Initially both pointer A and pointer B point to buffer A containing the initial DSP code. Each time the DSP requires execution of the configurable program, it reads pointer B, copies it to pointer A, and then branches to the buffer pointer A points to. When the host begins to relink to a buffer, it first sets pointer B equal to pointer A, relinks into the opposite buffer as pointer A, and then sets pointer B to this opposite buffer. The host is thereby prevented from updating a buffer currently being executed by the DSP. Real time dynamic linking of code segments in a tightly coupled co-processing system is thereby provided.

Claims

1. A system for dynamically linking code segments in real time, comprising

a first microprocessor;

a second microprocessor;

shared memory accessible by said first and second microprocessor comprising

a first buffer; and

a second buffer;

means for periodically causing code executable by said second microprocessor to be alternately updated in said shared memory by said first microprocessor;

a first state wherein a first portion of said code is updated in said first buffer by said first microprocessor while a second portion of said code is executed by said second microprocessor from said second buffer; and

a second state wherein a third portion of said code is updated in said second buffer by said first microprocessor while said first portion of said code is executed by said second microprocessor from said first buffer; and

pointer means indicating which of said first and second states said code is in.

3. The method of claim 1 wherein said first processor is a digital signal processor.

4. The method of claim 1 wherein said first processor is a microprocessor.

5. The method of claim 3 wherein said first code module corresponds to code executed by said digital signal processor causing said digital signal processor to generate acoustic data corresponding to a first sound.

6. The method of claim 5 wherein said second code module corresponds to code executed by the digital signal processor causing said digital signal processor to generate acoustic data corresponding to a second sound.

7. The method of claim 6 wherein said digital signal processor executes said first and second code modules from said first and second buffers alternately at a rate wherein said first and second sounds occur simultaneously.

2. A method for linking code segments in an asynchronous multiprocessor computer system accessing common shared memory comprised of first and second buffers, said method comprising the steps of:

executing a first code module in said shared memory by a first processor while asynchronously loading and linking code segments comprising a second code module in said shared memory by a second processor; and

executing said second code module with said first processor while asynchronously loading and linking code segments comprising a third code module in said shared memory with said second processor;

and wherein said method further includes

alternately executing code from said first and second buffers with said first processor;

loading and linking with said second processor at least one code module into said second buffer when said first processor executes code in said first buffer;

loading and linking with said second processor at least one code module into said first buffer when said first processor executes code in said second buffer;

setting a first pointer variable to an address location corresponding to one of said buffers which is being executed upon when said first processor is currently executing code; and

setting a second pointer variable to an address location corresponding to a remaining one of said buffers after being updated by said second processor with code segments comprising at least one code module loaded and linked by said second processor while said first processor is executing said code.

8. A method for dynamically linking code segments in an asynchronous computer system having a first and second processor and wherein said processors access shared memory having a first and second buffer, said method comprising the steps of

generating a first pointer variable pointing to one of said first and second buffers containing a first code module;

accessing said first pointer variable by said second processor to determine which one of said first and second buffers is being executed by said first processor;

storing and linking code segments comprising a second code module with said second processor in a remaining one of said first and second buffers with said second processor as a function of said accessing said first pointer variable and during execution of said first code module;

generating a second pointer variable;

accessing with said first processor said second pointer variable;

making a copy of the value of said second pointer variable with said first processor to said first pointer variable;

branching with said first processor to said one of said first or second buffers pointed to by said first pointer variable;

relinking with said second processor to said remaining one of said first and second buffers while said one of said first and second buffers is being asynchronously executed by said first microprocessor; and

asynchonously executing said remaining one of said first and second buffers after said relinking.

9. The method of claim 8 further comprising

setting said second pointer variable equal to said first pointer variable with said second processor;

relinking with said second processor into code segments of said remaining one of said first and second buffers; and

setting said second pointer variable to said remaining one of said first and second buffers.

10. A method for sharing memory in a multiprocessor system having a first and second multiprocessor and further having first and second shared buffers, comprising

generating a first and second pointer indicating, respectively, which of said first and second buffers is currently being executed by said second microprocessor and which of said first and second buffers is being updated by said first microprocessor;

storing code executable by said second microprocessor in said first buffer;

initializing said first and second pointers to point to said first buffer containing said executable code;

detecting when said second microprocessor requires execution of said code;

reading said second pointer by said second microprocessor in response to said detecting;

copying with said second microprocessor said second pointer to said first pointer;

branching by said second microprocessor to the one of said first and second buffers pointed to by said first pointer;

relinking by said first microprocessor to one of said first and second buffers;

executing code by said second microprocessor in an opposite one of said first and said second buffers concurrently with said relinking;

setting said second pointer with said first microprocessor equal to said first pointer;

relinking with said first microprocessor to said opposite one of said first or said second buffers from that pointed to by said first pointer; and

setting said second pointer to said opposite one of said first or said second buffers.